Neutrino-8B publish tree (cons3-B25 ship brain 016c6f36)

LICENSE

@@ -0,0 +1,202 @@
+                                 Apache License
+                           Version 2.0, January 2004
+                        http://www.apache.org/licenses/
+
+   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+   1. Definitions.
+
+      "License" shall mean the terms and conditions for use, reproduction,
+      and distribution as defined by Sections 1 through 9 of this document.
+
+      "Licensor" shall mean the copyright owner or entity authorized by
+      the copyright owner that is granting the License.
+
+      "Legal Entity" shall mean the union of the acting entity and all
+      other entities that control, are controlled by, or are under common
+      control with that entity. For the purposes of this definition,
+      "control" means (i) the power, direct or indirect, to cause the
+      direction or management of such entity, whether by contract or
+      otherwise, or (ii) ownership of fifty percent (50%) or more of the
+      outstanding shares, or (iii) beneficial ownership of such entity.
+
+      "You" (or "Your") shall mean an individual or Legal Entity
+      exercising permissions granted by this License.
+
+      "Source" form shall mean the preferred form for making modifications,
+      including but not limited to software source code, documentation
+      source, and configuration files.
+
+      "Object" form shall mean any form resulting from mechanical
+      transformation or translation of a Source form, including but
+      not limited to compiled object code, generated documentation,
+      and conversions to other media types.
+
+      "Work" shall mean the work of authorship, whether in Source or
+      Object form, made available under the License, as indicated by a
+      copyright notice that is included in or attached to the work
+      (an example is provided in the Appendix below).
+
+      "Derivative Works" shall mean any work, whether in Source or Object
+      form, that is based on (or derived from) the Work and for which the
+      editorial revisions, annotations, elaborations, or other modifications
+      represent, as a whole, an original work of authorship. For the purposes
+      of this License, Derivative Works shall not include works that remain
+      separable from, or merely link (or bind by name) to the interfaces of,
+      the Work and Derivative Works thereof.
+
+      "Contribution" shall mean any work of authorship, including
+      the original version of the Work and any modifications or additions
+      to that Work or Derivative Works thereof, that is intentionally
+      submitted to Licensor for inclusion in the Work by the copyright owner
+      or by an individual or Legal Entity authorized to submit on behalf of
+      the copyright owner. For the purposes of this definition, "submitted"
+      means any form of electronic, verbal, or written communication sent
+      to the Licensor or its representatives, including but not limited to
+      communication on electronic mailing lists, source code control systems,
+      and issue tracking systems that are managed by, or on behalf of, the
+      Licensor for the purpose of discussing and improving the Work, but
+      excluding communication that is conspicuously marked or otherwise
+      designated in writing by the copyright owner as "Not a Contribution."
+
+      "Contributor" shall mean Licensor and any individual or Legal Entity
+      on behalf of whom a Contribution has been received by Licensor and
+      subsequently incorporated within the Work.
+
+   2. Grant of Copyright License. Subject to the terms and conditions of
+      this License, each Contributor hereby grants to You a perpetual,
+      worldwide, non-exclusive, no-charge, royalty-free, irrevocable
+      copyright license to reproduce, prepare Derivative Works of,
+      publicly display, publicly perform, sublicense, and distribute the
+      Work and such Derivative Works in Source or Object form.
+
+   3. Grant of Patent License. Subject to the terms and conditions of
+      this License, each Contributor hereby grants to You a perpetual,
+      worldwide, non-exclusive, no-charge, royalty-free, irrevocable
+      (except as stated in this section) patent license to make, have made,
+      use, offer to sell, sell, import, and otherwise transfer the Work,
+      where such license applies only to those patent claims licensable
+      by such Contributor that are necessarily infringed by their
+      Contribution(s) alone or by combination of their Contribution(s)
+      with the Work to which such Contribution(s) was submitted. If You
+      institute patent litigation against any entity (including a
+      cross-claim or counterclaim in a lawsuit) alleging that the Work
+      or a Contribution incorporated within the Work constitutes direct
+      or contributory patent infringement, then any patent licenses
+      granted to You under this License for that Work shall terminate
+      as of the date such litigation is filed.
+
+   4. Redistribution. You may reproduce and distribute copies of the
+      Work or Derivative Works thereof in any medium, with or without
+      modifications, and in Source or Object form, provided that You
+      meet the following conditions:
+
+      (a) You must give any other recipients of the Work or
+          Derivative Works a copy of this License; and
+
+      (b) You must cause any modified files to carry prominent notices
+          stating that You changed the files; and
+
+      (c) You must retain, in the Source form of any Derivative Works
+          that You distribute, all copyright, patent, trademark, and
+          attribution notices from the Source form of the Work,
+          excluding those notices that do not pertain to any part of
+          the Derivative Works; and
+
+      (d) If the Work includes a "NOTICE" text file as part of its
+          distribution, then any Derivative Works that You distribute must
+          include a readable copy of the attribution notices contained
+          within such NOTICE file, excluding those notices that do not
+          pertain to any part of the Derivative Works, in at least one
+          of the following places: within a NOTICE text file distributed
+          as part of the Derivative Works; within the Source form or
+          documentation, if provided along with the Derivative Works; or,
+          within a display generated by the Derivative Works, if and
+          wherever such third-party notices normally appear. The contents
+          of the NOTICE file are for informational purposes only and
+          do not modify the License. You may add Your own attribution
+          notices within Derivative Works that You distribute, alongside
+          or as an addendum to the NOTICE text from the Work, provided
+          that such additional attribution notices cannot be construed
+          as modifying the License.
+
+      You may add Your own copyright statement to Your modifications and
+      may provide additional or different license terms and conditions
+      for use, reproduction, or distribution of Your modifications, or
+      for any such Derivative Works as a whole, provided Your use,
+      reproduction, and distribution of the Work otherwise complies with
+      the conditions stated in this License.
+
+   5. Submission of Contributions. Unless You explicitly state otherwise,
+      any Contribution intentionally submitted for inclusion in the Work
+      by You to the Licensor shall be under the terms and conditions of
+      this License, without any additional terms or conditions.
+      Notwithstanding the above, nothing herein shall supersede or modify
+      the terms of any separate license agreement you may have executed
+      with Licensor regarding such Contributions.
+
+   6. Trademarks. This License does not grant permission to use the trade
+      names, trademarks, service marks, or product names of the Licensor,
+      except as required for reasonable and customary use in describing the
+      origin of the Work and reproducing the content of the NOTICE file.
+
+   7. Disclaimer of Warranty. Unless required by applicable law or
+      agreed to in writing, Licensor provides the Work (and each
+      Contributor provides its Contributions) on an "AS IS" BASIS,
+      WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+      implied, including, without limitation, any warranties or conditions
+      of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A
+      PARTICULAR PURPOSE. You are solely responsible for determining the
+      appropriateness of using or redistributing the Work and assume any
+      risks associated with Your exercise of permissions under this License.
+
+   8. Limitation of Liability. In no event and under no legal theory,
+      whether in tort (including negligence), contract, or otherwise,
+      unless required by applicable law (such as deliberate and grossly
+      negligent acts) or agreed to in writing, shall any Contributor be
+      liable to You for damages, including any direct, indirect, special,
+      incidental, or consequential damages of any character arising as a
+      result of this License or out of the use or inability to use the
+      Work (including but not limited to damages for loss of goodwill,
+      work stoppage, computer failure or malfunction, or any and all
+      other commercial damages or losses), even if such Contributor
+      has been advised of the possibility of such damages.
+
+   9. Accepting Warranty or Additional Liability. While redistributing
+      the Work or Derivative Works thereof, You may choose to offer,
+      and charge a fee for, acceptance of support, warranty, indemnity,
+      or other liability obligations and/or rights consistent with this
+      License. However, in accepting such obligations, You may act only
+      on Your own behalf and on Your sole responsibility, not on behalf
+      of any other Contributor, and only if You agree to indemnify,
+      defend, and hold each Contributor harmless for any liability
+      incurred by, or claims asserted against, such Contributor by reason
+      of your accepting any such warranty or additional liability.
+
+   END OF TERMS AND CONDITIONS
+
+   APPENDIX: How to apply the Apache License to your work.
+
+      To apply the Apache License to your work, attach the following
+      boilerplate notice, with the fields enclosed by brackets "{}"
+      replaced with your own identifying information. (Don't include
+      the brackets!)  The text should be enclosed in the appropriate
+      comment syntax for the file format. We also recommend that a
+      file or class name and description of purpose be included on the
+      same "printed page" as the copyright notice for easier
+      identification within third-party archives.
+
+   Copyright 2026 Fermion Research
+
+   Licensed under the Apache License, Version 2.0 (the "License");
+   you may not use this file except in compliance with the License.
+   You may obtain a copy of the License at
+
+       http://www.apache.org/licenses/LICENSE-2.0
+
+   Unless required by applicable law or agreed to in writing, software
+   distributed under the License is distributed on an "AS IS" BASIS,
+   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+   See the License for the specific language governing permissions and
+   limitations under the License.
+

MANIFEST.json

@@ -0,0 +1,335 @@
+{
+  "note": "provenance: HF-tree filename -> source + sha256; weights entry is declarative until materialized | upload lane 2026-07-27: __pycache__/*.pyc excluded from the published tree (not-for-shipping)",
+  "weights_container": {
+    "file": "neutrino-8b_v4.bin",
+    "status": "FINAL \u2014 cons3-B25 SHIP BRAIN (consolidation-3 arm B step 25, FOUNDER-AUTHORISED PROMOTE 2026-07-27 ~19:50 IST: GSM8K stated 49.33 / flexible 51.00 / BFCL 65.31 / IFEval-ps 73.17 / MMLU-Redux 67.84 / full-57 72.084 / C4 21.475 / term 0.5067. The Redux no-regression guard (69.5) was breached at 67.84 and the founder amended the bar on the record \u2014 see handoffs/RESEARCH_LEDGER.md. Supersedes ifc-s50 39787a2e\u2026a3be)",
+    "bytes": 3875404812,
+    "sha256": "016c6f362ad237a8cf4043601efbc1e766574f76ea58691e78fdef51b4155fa0",
+    "source": "internal lab archive: archive/consolidation_3/export_v4_B25/neutrino-8b_v4.bin (public copy: huggingface.co/fermionresearch/Neutrino-8B)",
+    "qat_state_sha256": "09c3f36a72e73223f79e4d7c6fd82295ecc09eb7d81f027afbd239f26f9441b8",
+    "coded_transport": {
+      "file": "neutrino-8b_v4.tv4z",
+      "bytes": 2559836297,
+      "sha256": "83ec7a52bd6733e66fb546e89b9c6aa8b3411af7f648e9c0b2bb56ba50aac4df",
+      "note": "lossless tv4z transport, 66.05% of raw; decode round-trip md5/sha/cmp PASS"
+    },
+    "retired_do_not_verify_against": {
+      "ifc-s50 container": "39787a2e15dcffa20135c7c1bb1b8ed55c8632263f8457f3395f55d52007a3be",
+      "ifc-s50 tv4z": "7d36adaf18c5d779aa96d09a6a6eb080eec39bc8b7dcc8a5eb6680f8fc134c7a",
+      "ifc-s50 qat_state": "e62a1199f83285f60352ede2ec9255dbcbc468976e5c8b9595536717260fb6a9",
+      "ifc-s50 gguf": "7dda995047dc70540d2d83f2c464dd118fff62eef1aab36ae71ceb3cc972e5d0"
+    }
+  },
+  "files": {
+    ".gitattributes": {
+      "bytes": 1905,
+      "sha256": "501edc5292358aaa11dd13cd5e9b25c43f94df3cc9fff43dd3c0df50efcc40c0",
+      "source": "banked lane artifact (LFS globs made explicit per-file 2026-07-27 upload lane)"
+    },
+    "LICENSE": {
+      "bytes": 11347,
+      "sha256": "2f978a54ef89f3e4ee2d413c347e4b03500c95f29342277a287acc2ae27ae280",
+      "source": "Apache-2.0 text (same file across all release trees)"
+    },
+    "NOTICE": {
+      "bytes": 1557,
+      "sha256": "a17bda9d5b1e7d90927a39a2b7c2e40a5cb8afe36ecb9f8c776802cec75b04ca",
+      "source": "banked lane artifact"
+    },
+    "bin/README.md": {
+      "bytes": 7211,
+      "sha256": "172b910ceb503f28b8bd1977e805d3cd04024192625b31ef1899a30b8e8d6c88",
+      "source": "bin/ staging doc: which fermion-run binaries land at upload + sidecar convention"
+    },
+    "bin/fermion-run-linux-x64": {
+      "bytes": 1249584,
+      "sha256": "499ecdc569eae2ceaeb4a34cd1f11a91c2c09dfb17aa5847532359c6dc57d93a",
+      "source": "BLESSED release binary (Linux x86-64 AVX2 baseline, fully static) \u2014 release-binaries lane 2026-07-25, receipt handoffs/results_release_binaries/receipt_linux_x64.json"
+    },
+    "bin/fermion-run-linux-x64.sha256": {
+      "bytes": 88,
+      "sha256": "2350e759fe77faa43803b43ab72f5c3bf2ca12263dddc680af6e453381f2649c",
+      "source": "sha256 sidecar (shasum line) for fermion-run-linux-x64"
+    },
+    "bin/fermion-run-macos-arm64": {
+      "bytes": 621480,
+      "sha256": "d7b257b5cd4b08cadd04fd867158ac50619aab23164294794dc10f05f1ede53c",
+      "source": "BLESSED release binary (macOS arm64 CPU/NEON, static libomp) \u2014 release-binaries lane 2026-07-25, receipt handoffs/results_release_binaries/receipt_macos_arm64.json"
+    },
+    "bin/fermion-run-macos-arm64.sha256": {
+      "bytes": 90,
+      "sha256": "d706f6935e715a96df3736035fb22ffa7854a8cb337b575542cd03ecb281ef72",
+      "source": "sha256 sidecar (shasum line) for fermion-run-macos-arm64"
+    },
+    "config.json": {
+      "bytes": 505,
+      "sha256": "4779738d791ad490794f6b0a7e04c1cb50f2720fbe8b6503c61da547c0861c0a",
+      "source": "written for the trtc_v4 loader (hf_ternary registration)"
+    },
+    "generation_config.json": {
+      "bytes": 181,
+      "sha256": "2537909d4312b7155b60fe0aee96d342de1a00b7841ed3e7eba4c3835d16d8ae",
+      "source": "transformers generation defaults for this SKU"
+    },
+    "gguf/Modelfile": {
+      "bytes": 214,
+      "sha256": "47c4c5ac0228e25197eb52e1ae0a964f95ac0d562d9effe9547f01c0cb58a9d1",
+      "source": "banked lane artifact"
+    },
+    "gguf/README.md": {
+      "bytes": 10315,
+      "sha256": "0124d20fe1e1af892cd809bbcc0a9d390d687684c0747bc6ca8a0b9e12280ce2",
+      "source": "banked lane artifact"
+    },
+    "gguf/SHA256SUMS": {
+      "bytes": 1912,
+      "sha256": "457e700fc5db35c5618a7c61dc0e4ac601d94f12ed264374b0717c574275bfc4",
+      "source": "banked lane artifact"
+    },
+    "gguf/receipts/bench_8b.json": {
+      "bytes": 2663,
+      "sha256": "1976449e3aa06f21e8337d0035ce8ee8371d6ff94d84adbafd149dbfa3f9d6fb",
+      "source": "banked lane artifact"
+    },
+    "gguf/receipts/convert_8b.json": {
+      "bytes": 953,
+      "sha256": "09060b46412b45b856edd239c37b49208f7cebb153620dda1808296ace8308ea",
+      "source": "banked lane artifact"
+    },
+    "gguf/receipts/gate_8b_fv5.json": {
+      "bytes": 6989,
+      "sha256": "393e6d48d74c27bca09ce82af855a1d5917347595477c4587774d0391b305e34",
+      "source": "banked lane artifact"
+    },
+    "gguf/receipts/gateverdict_8b_fv5.json": {
+      "bytes": 457,
+      "sha256": "cd79e09be62309d4146da1530211529a9b98cffed0e240c7ef30c7466f8a64c1",
+      "source": "banked lane artifact"
+    },
+    "gguf/receipts/gguf_spec_quickstart_k16.json": {
+      "bytes": 9857,
+      "sha256": "50079ec10a6b1b1eaf131a2955a2d409d5c1b35926aa12a94e7789ff9bd11962",
+      "source": "banked lane artifact"
+    },
+    "gguf/receipts/gguf_spec_quickstart_k4.json": {
+      "bytes": 9830,
+      "sha256": "a2ef2374d6affde8ec47560ff146d44da8170c939d55c82d32fea653ae5e3da2",
+      "source": "banked lane artifact"
+    },
+    "gguf/receipts/ref_8b.json": {
+      "bytes": 470,
+      "sha256": "8916c4936da50ca500f521a19ce4d69668e8fd5603588113359efba5a059851a",
+      "source": "banked lane artifact"
+    },
+    "gguf/receipts_ifcs50_retired/bench_8b.json": {
+      "bytes": 2656,
+      "sha256": "348dccfc95f896beaacaf7297df7574b364e4d6a431bc54a34f4737fb39acdd8",
+      "source": "banked lane artifact"
+    },
+    "gguf/receipts_ifcs50_retired/convert_8b.json": {
+      "bytes": 947,
+      "sha256": "111e69bfcf5cea559dfcd500c58b07db366cd1c26cd2c27be49dcf1d645f940a",
+      "source": "banked lane artifact"
+    },
+    "gguf/receipts_ifcs50_retired/gateverdict_8b_fv5.json": {
+      "bytes": 457,
+      "sha256": "2f45fb6b747cb2ac8e3910bc4e929caad78660485e329eb1828095cb2dff5fa4",
+      "source": "banked lane artifact"
+    },
+    "gguf/receipts_ifcs50_retired/ref_8b.json": {
+      "bytes": 470,
+      "sha256": "0eb0e2485f3b5aa3c303e33200112cde1fd5441642e440ee1d7e5e5f4821966e",
+      "source": "banked lane artifact"
+    },
+    "merges.txt": {
+      "bytes": 1671853,
+      "sha256": "8831e4f1a044471340f7c0a83d7bd71306a5b867e95fd870f74d0c5308a904d5",
+      "source": "Qwen/Qwen3-8B tokenizer file (Apache-2.0 upstream)"
+    },
+    "mlx/MANIFEST.json": {
+      "bytes": 6950,
+      "sha256": "f87359d53dfd9f433a86495bd87759c1faeaf09b12cf07f9a06d4ec00e7619f5",
+      "source": "banked lane artifact"
+    },
+    "mlx/README.md": {
+      "bytes": 6201,
+      "sha256": "4d3a3dbc7ab1d32df93a72a1ca1e90b98af9c99c6a3ecd0d1af468d37fa7a278",
+      "source": "banked lane artifact"
+    },
+    "mlx/fermion_mlx/__init__.py": {
+      "bytes": 5004,
+      "sha256": "9d96d2fe71a8d1af20d78dc2d1cf016d01175462712aed36d493d82d3ffca87e",
+      "source": "banked lane artifact"
+    },
+    "mlx/fermion_mlx/__main__.py": {
+      "bytes": 8066,
+      "sha256": "aac000379d0c5cab04f5d6bbcb080e20c987cd87c60e8e0d3ad0a87e389937fc",
+      "source": "banked lane artifact"
+    },
+    "mlx/fermion_mlx/arch3.py": {
+      "bytes": 7541,
+      "sha256": "a831e8a24b2b9a986b393d1c316aac66a3399a082a57176254b2feeae032f8cd",
+      "source": "banked lane artifact"
+    },
+    "mlx/fermion_mlx/container.py": {
+      "bytes": 6059,
+      "sha256": "c5b352184ba9ddf9a3e424731226cb7dcb9901d3a1516c67d4557953b0101f2f",
+      "source": "banked lane artifact"
+    },
+    "mlx/fermion_mlx/gates.py": {
+      "bytes": 7454,
+      "sha256": "faf8634b0bd3afec5c4422decdbd8cc04fbb7f3426f70cdd6626fd6b177aa8b4",
+      "source": "banked lane artifact"
+    },
+    "mlx/fermion_mlx/mbatch.py": {
+      "bytes": 6492,
+      "sha256": "c9ec8d37f1cdc0554cda01cefbc435e67525779c79e0dac7fd760e7919e6fdd2",
+      "source": "banked lane artifact"
+    },
+    "mlx/fermion_mlx/model.py": {
+      "bytes": 12748,
+      "sha256": "9488f8194ce8be006ce05dfaf6118353de44005ce54f38f73a0908ccac2749da",
+      "source": "banked lane artifact"
+    },
+    "mlx/fermion_mlx/spec.py": {
+      "bytes": 11207,
+      "sha256": "969e946d5d2eeb63d44afa4c62dd2453d87fa14e83b936bc673482b59ee3b745",
+      "source": "banked lane artifact"
+    },
+    "mlx/fermion_mlx/trit_kernels.py": {
+      "bytes": 36881,
+      "sha256": "c56db6dd5e3743d19c54411f5f0b2dfef135f7805906a62cc4e40f1ee5e80f27",
+      "source": "banked lane artifact"
+    },
+    "mlx/merges.txt": {
+      "bytes": 1671853,
+      "sha256": "8831e4f1a044471340f7c0a83d7bd71306a5b867e95fd870f74d0c5308a904d5",
+      "source": "banked lane artifact"
+    },
+    "mlx/receipts/bench_8b_wbase_m5_16gb_memcapped.json": {
+      "bytes": 599,
+      "sha256": "9d3b153ec49dce92846fb9140fc38267ed04a08b5adcda91f2036ce94869b555",
+      "source": "banked lane artifact"
+    },
+    "mlx/receipts/pathgate_8b_cons3b25.json": {
+      "bytes": 634,
+      "sha256": "ff7f68d926d381a6c1a00f07cbb33ad5b3ac118d7b9dd997de0857cc1af40f71",
+      "source": "banked lane artifact"
+    },
+    "mlx/receipts/pathgate_8b_d25.json": {
+      "bytes": 631,
+      "sha256": "0de2306ce8c15c80fb776b2d73e6d056302d1d7367440e2c567d4370aaeef81c",
+      "source": "banked lane artifact"
+    },
+    "mlx/receipts/pathgate_8b_product.json": {
+      "bytes": 633,
+      "sha256": "c13e35c461c6e3a23fb2976d0f26f0b8dce114b12bf976a05cb19f11cc0746ea",
+      "source": "banked lane artifact"
+    },
+    "mlx/receipts/pathgate_8b_wbase.json": {
+      "bytes": 612,
+      "sha256": "50d6584a9ba2dae87bf502f2e637916a604be72db473fc89977fb8e1aaf3413b",
+      "source": "banked lane artifact"
+    },
+    "mlx/receipts/refgate_8b_cons3b25.json": {
+      "bytes": 1916,
+      "sha256": "d5a072dd5f796e8fa87269b0a44b3f525de627bb9ee79adeb7fcf973efcb00d7",
+      "source": "banked lane artifact (local absolute model path redacted to basename 2026-07-27 upload lane)"
+    },
+    "mlx/receipts/refgate_8b_d25.json": {
+      "bytes": 1918,
+      "sha256": "ece57b474473c07bb4064279b73a6f4aa199deb055b39e8166c86cd41a2a71b2",
+      "source": "banked lane artifact"
+    },
+    "mlx/receipts/refgate_8b_product.json": {
+      "bytes": 1919,
+      "sha256": "5b194b6fb22534c2c9f61cc48be7d5e1ace92b77cd3edb136ed88f94fd0bf2a3",
+      "source": "banked lane artifact"
+    },
+    "mlx/receipts/refgate_8b_wbase.json": {
+      "bytes": 1909,
+      "sha256": "851da3bb5c093182eb56532711dd9a95123ca44260e53de951b27c8b96eaf7a4",
+      "source": "banked lane artifact"
+    },
+    "mlx/receipts/specbench_8b_0p6b_m5.json": {
+      "bytes": 826,
+      "sha256": "c36ef09659d8c7690d53c23d065943103a95417890f8defbd01e629d7b5feeca",
+      "source": "banked lane artifact"
+    },
+    "mlx/receipts/specgate_8b_0p6b.json": {
+      "bytes": 705,
+      "sha256": "64bcb90fe965835bc78887d873d3cfd0677b76c6d72cda04a84e295efee7c10c",
+      "source": "banked lane artifact"
+    },
+    "mlx/requirements.txt": {
+      "bytes": 191,
+      "sha256": "1cf4d1fa581aaa5deae0568f88388c51166bbd69e7a89080b5a53488a7ef39b6",
+      "source": "banked lane artifact"
+    },
+    "mlx/tokenizer.json": {
+      "bytes": 11422654,
+      "sha256": "aeb13307a71acd8fe81861d94ad54ab689df773318809eed3cbe794b4492dae4",
+      "source": "banked lane artifact"
+    },
+    "mlx/tokenizer_config.json": {
+      "bytes": 9732,
+      "sha256": "d5d09f07b48c3086c508b30d1c9114bd1189145b74e982a265350c923acd8101",
+      "source": "banked lane artifact"
+    },
+    "mlx/vocab.json": {
+      "bytes": 2776833,
+      "sha256": "ca10d7e9fb3ed18575dd1e277a2579c16d108e32f27439684afa0e10b1440910",
+      "source": "banked lane artifact"
+    },
+    "receipts/acceptance_receipt_d25.json": {
+      "bytes": 9820,
+      "sha256": "037e3c009d6287ecd0f3dfcd38065236b832e63d7c0d64f5124fbde46a1816c3",
+      "source": "banked lane artifact"
+    },
+    "receipts/acceptance_receipt_s50.json": {
+      "bytes": 9772,
+      "sha256": "b46a60823b86f8f1f1f0d119492ae19b6a2ac667c5a98733721a6118eeed4da5",
+      "source": "banked lane artifact"
+    },
+    "receipts/dspec_cert_cons3_b25.json": {
+      "bytes": 6061,
+      "sha256": "086607c20ada9bc1ec251e217329e6ec5146f3826d6f4feab5e918e1b346240f",
+      "source": "banked lane artifact"
+    },
+    "receipts/dspec_cert_ifc_s50.json": {
+      "bytes": 700,
+      "sha256": "d5f8b115759e4abac8e9856a6c771ddb68c5eeadf9fc0af8f69062a349032bf8",
+      "source": "banked lane artifact"
+    },
+    "receipts/dspec_cert_ifc_s50.json.log": {
+      "bytes": 2130,
+      "sha256": "91fab18237b4b6fa465f9f90cb4a83c97918cc92d0def8f08b50fff45d7d475e",
+      "source": "banked lane artifact"
+    },
+    "receipts/export_receipts_d25.json": {
+      "bytes": 5890,
+      "sha256": "0a77b6c649bcbda96a52730f7daee2d8e47ee3b8c3c0485ee9b2db9d6cc0faf0",
+      "source": "banked lane artifact"
+    },
+    "receipts/export_receipts_s50.json": {
+      "bytes": 5959,
+      "sha256": "909f92d30e37f99ea78e2990904749213e1c4bbeaa01a0250f79d5a2b8f9b201",
+      "source": "banked lane artifact"
+    },
+    "tokenizer.json": {
+      "bytes": 11422654,
+      "sha256": "aeb13307a71acd8fe81861d94ad54ab689df773318809eed3cbe794b4492dae4",
+      "source": "Qwen/Qwen3-8B tokenizer file (Apache-2.0 upstream)"
+    },
+    "tokenizer_config.json": {
+      "bytes": 9732,
+      "sha256": "d5d09f07b48c3086c508b30d1c9114bd1189145b74e982a265350c923acd8101",
+      "source": "Qwen/Qwen3-8B tokenizer file (Apache-2.0 upstream)"
+    },
+    "vocab.json": {
+      "bytes": 2776833,
+      "sha256": "ca10d7e9fb3ed18575dd1e277a2579c16d108e32f27439684afa0e10b1440910",
+      "source": "Qwen/Qwen3-8B tokenizer file (Apache-2.0 upstream)"
+    }
+  }
+}

NOTICE

@@ -0,0 +1,43 @@
+Neutrino — Fermion Research
+Copyright 2026 Fermion Research
+
+This product includes software and model artifacts developed by
+Fermion Research, licensed under the Apache License, Version 2.0
+(see LICENSE).
+
+--------------------------------------------------------------------
+THIRD-PARTY NOTICES
+--------------------------------------------------------------------
+
+Qwen3 (Alibaba Cloud / Qwen Team)
+Copyright (c) Alibaba Cloud
+Licensed under the Apache License, Version 2.0
+https://huggingface.co/Qwen/Qwen3-8B
+
+This model is a derivative of Qwen/Qwen3-8B. In particular, the following
+files in this repository are redistributed VERBATIM from the upstream
+Qwen3 release and are covered by Alibaba Cloud's copyright and the
+Apache License 2.0:
+
+  tokenizer.json
+  tokenizer_config.json
+  vocab.json
+  merges.txt
+
+The model architecture is stock Qwen3 geometry. The ternary
+quantization-aware training, the TRTC v4 container format, the
+post-training, the runtimes and the evaluation receipts are Fermion
+Research's own work.
+
+You may obtain a copy of the Apache License 2.0 at:
+  http://www.apache.org/licenses/LICENSE-2.0
+
+--------------------------------------------------------------------
+
+llama.cpp (The ggml authors) — MIT License
+
+The GGUF pack in gguf/ is produced for, and loaded by, Fermion
+Research's fork of ggml-org/llama.cpp. That fork is distributed
+separately under upstream's MIT license, NOT under this repository's
+Apache-2.0 grant. Any patch or source in gguf/ that derives from
+llama.cpp is MIT-licensed; see the fork's own LICENSE.

README.md

@@ -0,0 +1,558 @@
+---
+license: apache-2.0
+base_model: Qwen/Qwen3-8B
+pipeline_tag: text-generation
+library_name: transformers
+tags:
+  - ternary
+  - sub-2-bit
+  - quantization
+  - trtc
+---
+
+> [!WARNING]
+> **[MMLU-adapted, disclosed] This model was deliberately trained on the
+> public MMLU test, validation, dev, and auxiliary-train splits** (all
+> 115,700 public `cais/mmlu` rows) as part of its shipping recipe, and we
+> say so up front. **Its MMLU-family scores (72.1-class) are not comparable
+> to clean models and must not be quoted as benchmark results without this
+> label.** Clean-lineage calibration anchors (internal checkpoints, not
+> products): full-57 63.43 / 63.99, blind MMLU-CF 52.74 / 53.61. On the
+> blind, contamination-free meter the adaptation bought approximately
+> nothing (adapted brain W-7500: 54.32; sibling arm W-7000: 54.16; clean
+> branch: 53.61) — which is the point, and the method + receipts are
+> published in the eval-receipts repo.
+
+# Neutrino-8B
+
+An 8B chat model whose every transformer linear is stored **five-valued
+(sub-2 bits per weight)** in a single 3.88 GB (3.61 GiB) container, and
+which loads as a native `transformers` model in one `from_pretrained` call.
+
+This is the ONE published 8B SKU, and it is the full release stack:
+the MMLU-adapted brain (W step 7500, disclosed above) → the combined
+behavior stage → the IF-1 instruction stack, snapshot-50 → the
+verifiable-reward tool-calling stage, dose-25, locked 2026-07-26 after
+passing all release guards plus the tool-calling primary and stretch
+targets (VERDICT PASS, `results_bfcl_round2/r2_summary.json`). There is
+no separate "clean" variant to download; the clean lineage exists only
+as internal calibration anchors in the published tables. Cross-model
+rows we publish are same-harness measurements, and every 72.1-class
+knowledge cell carries the adaptation label wherever it appears.
+
+- Container: `neutrino-8b_v4.bin` — TRTC v4, arch-3 (Qwen3 topology),
+  36 layers, hidden 4096, vocab 151936.
+  **Product bake landed (cons3-B25, the ship brain)**: baked 2026-07-27
+  from the consolidation-3 arm-B dose-25 QAT state — the ifc-s50 brain
+  plus 25 steps of a three-axis consolidation diet (stated-format math KD,
+  live-checker instruction following, gold function-calling). It buys the
+  GSM8K stated-format column and trades MMLU-Redux; the Redux
+  no-regression guard was breached and deliberately amended by the
+  founder on the record (`results_consolidation_3/RESULTS.md`).
+  3,875,404,812 bytes, sha256
+  `016c6f362ad237a8cf4043601efbc1e766574f76ea58691e78fdef51b4155fa0`.
+  <!-- Retirement record (receipts culture; internal archive locations are
+  not published). Superseded: earlier product bake — baked 2026-07-25
+  (banked 23:31Z) from the IF-stack snap50 QAT state (Manan lock 2026-07-25
+  23:51 IST), 3,875,404,812 bytes, sha256
+  fe85f93214376354f118a83235eeff6bc5d40e112474afacbd3e0310768b08d5, under
+  archive/if_stack_b800/export_v4/. Earlier still, same culture: interim
+  development container (stage-B step-800 bake, 3,875,404,812 bytes, sha256
+  be44129e579a1c39d713652a0a4f3dd046e61dab83524d023d2f238ef181b814), which
+  carried the pre-launch working slug at source. -->
+- Inside: 252 packed trit linears + int8 embedding lanes (untied). Nothing
+  in the decode path is fp16/fp32 weights; scales are snapped to the
+  runtime grid at export.
+- Base: [Qwen/Qwen3-8B](https://huggingface.co/Qwen/Qwen3-8B) (Apache-2.0),
+  ternary QAT + staged post-training by [Fermion Research](https://huggingface.co/fermionresearch).
+  Tokenizer: Qwen3-8B (shipped in this repo).
+
+## Architecture
+
+Geometry as read from the shipped container's header (bit-checked during
+the GGUF conversion, `gguf/receipts/convert_8b.json`; byte budget from the
+provenance-gated container walk, `results_model_anatomy/ANATOMY.json`):
+
+| field | value |
+|---|---|
+| Parameters | 8,190,735,360 (6,945,767,424 ternary projection + 1,244,659,712 int8 embedding + 308,224 fp32 norm) |
+| Decoder layers | 36 |
+| Hidden width | 4,096 |
+| Feed-forward width | 12,288, gated (SwiGLU) |
+| Attention | grouped-query 4:1 — 32 query heads, 8 KV heads, head_dim 128 |
+| Rotary embedding | full head width (rotary_dims 128), theta 1,000,000 |
+| Normalization | RMSNorm, eps 1e-6, plus per-head Q/K RMSNorm in attention |
+| Context length | 40,960 tokens (`max_pos`) |
+| Vocabulary | 151,936 |
+| Embeddings | untied — separate int8 input-embedding and lm_head records |
+| KV cache | 144 KiB/token fp16 (288 KiB fp32): 0.60 GB @ 4k, 4.83 GB @ 32k |
+
+Byte budget of the 3,875,404,812-byte container, by tensor class:
+
+| lane | bytes | share |
+|---|---:|---:|
+| ternary weight lane (q/k/v/o/gate/up/down × 36 layers = 252 linears) | 2,604,662,784 | 67.2% |
+| token embeddings, int8 (two untied 622 MB records) | 1,244,659,712 | 32.1% |
+| per-row metadata (dims, scales, row sums) | 24,849,360 | 0.6% |
+| norm vectors, fp32 (145 tensors) | 1,232,896 | 0.03% |
+| container header | 60 | — |
+
+Every layer costs exactly 72,351,744 weight-lane bytes (21.7% attention /
+78.3% MLP). State occupancy across the 6.95B ternary weights: 62.63% zero /
+18.68% plus / 18.69% minus (per-layer arrays in ANATOMY.json).
+
+## Formats and artifacts
+
+| artifact | bytes | sha256 |
+|---|---:|---|
+| `neutrino-8b_v4.bin` (TRTC v4 container, the file every runtime executes) | 3,875,404,812 | `016c6f362ad237a8cf4043601efbc1e766574f76ea58691e78fdef51b4155fa0` |
+| `neutrino-8b_v4.tv4z` (lossless coded transport, 66.05% of raw) | 2,559,836,297 | `83ec7a52bd6733e66fb546e89b9c6aa8b3411af7f648e9c0b2bb56ba50aac4df` |
+| `gguf/neutrino-8b-fv5.gguf` (llama.cpp-fork pack, bit-checked vs the container) | 4,093,015,136 | `7dda995047dc70540d2d83f2c464dd118fff62eef1aab36ae71ceb3cc972e5d0` |
+
+The tv4z transport decodes back to the container byte-exactly (md5+sha
+round-trip identity, `results_tv4z_8b_ship/RESULTS.md`; 17 s encode / 6 s
+decode on an M5). Three distribution surfaces read these artifacts:
+
+1. **pip engine** (`pip install fermion`) — the one-command door; pulls the
+   container and the platform-matching `bin/` runtime from this repo.
+   Measured: 24.94 tok/s CPU-only on an Apple M5, 9 threads.
+2. **GGUF pack + our llama.cpp fork** (`gguf/`) — ecosystem door for
+   llama.cpp / ollama / LM Studio, CPU + CUDA. Measured: 30.7 tok/s on an
+   NVIDIA L4 at full offload, 4.68 GiB VRAM @ 4k context (fits 8 GB cards).
+3. **MLX pack** (`mlx/`) — Python-native Apple-silicon runtime with custom
+   Metal kernels. Measured: 25.0 tok/s median on a 16 GB M5 under a 6 GiB
+   memory cap.
+
+## Quickstart
+
+```bash
+pip install fermion
+printf 'In one sentence, why is the sky blue?\n/exit\n' | \
+  fermion chat --model fermionresearch/Neutrino-8B --max-new 48
+```
+
+Or pure `transformers`:
+
+```python
+import fermion  # registers the trtc_v4 model type
+from transformers import AutoModelForCausalLM, AutoTokenizer
+
+model = AutoModelForCausalLM.from_pretrained("fermionresearch/Neutrino-8B")
+tokenizer = AutoTokenizer.from_pretrained("fermionresearch/Neutrino-8B")
+inputs = tokenizer.apply_chat_template([{"role": "user", "content": "hi"}],
+                                       add_generation_prompt=True,
+                                       enable_thinking=False,
+                                       return_tensors="pt", return_dict=True)
+out = model.generate(**inputs, max_new_tokens=256)  # generation_config: greedy
+n = inputs["input_ids"].shape[1]
+print(tokenizer.decode(out[0][n:], skip_special_tokens=True))
+```
+
+`import fermion` must come first: it is what registers the `trtc_v4` model
+type, and without it `AutoTokenizer`/`AutoModelForCausalLM` cannot read this
+repo's `config.json`. `return_dict=True` is not optional either on
+transformers 4.56 and newer, where `apply_chat_template` returns a mapping
+rather than a bare tensor.
+
+`generation_config.json` in this repo is deliberately **greedy with no
+repetition penalty and no top-k**: that is the setting the published MMLU,
+GSM8K, IFEval and BFCL numbers were measured at, so a bare `generate()`, an
+`lm-eval` run and `fermion generate` all reproduce each other. The
+conversational and long-form settings are one argument away — see
+[Recommended settings](#recommended-settings-by-use-case).
+
+GGUF surface (build our fork once, then standard llama.cpp tooling —
+full instructions in `gguf/README.md`):
+
+```bash
+git clone https://github.com/ggml-org/llama.cpp && cd llama.cpp
+git checkout d67c0b4107112e4790774c3a8169e2e3eb24643b && git am fv5.patch
+cmake -B build -DCMAKE_BUILD_TYPE=Release && cmake --build build -j --target llama-cli
+./build/bin/llama-cli -m neutrino-8b-fv5.gguf -p "Why is the sky blue?" -n 256 --temp 0
+```
+
+MLX surface (Apple silicon — full instructions in `mlx/README.md`):
+
+```bash
+pip install -r mlx/requirements.txt
+python -m fermion_mlx --model neutrino-8b_v4.bin --mode chat \
+    --tokenizer . --prompt "Why is the sky blue?"
+```
+
+The pip path is the **reference torch path**: correctness-gated (bit-packed
+weights at rest, 0 greedy mismatches vs the native runtime over 768 tokens;
+receipt in the eval-receipts repo), honest about speed — it is NOT the fast
+path. The fast path ships **in this repo** under `bin/` (see below).
+
+Verified end-to-end in one fresh CPU container (Modal, cpu=8, 24 GiB, no
+GPU): wheel install -> container sha gate -> piped `chat` produced a
+real answer; receipt: `receipts/acceptance_cpu_receipt_20260724.json`
+(run under the pre-rename working slug; same code path, wheel renamed
+`fermion` and repo id renamed `Neutrino-8B` 2026-07-24 per the release
+runbook). Peak resident memory for load+chat was under 8 GiB (bit-packed
+weights). Acceptance rerun against the final product container is a
+publish gate (RELEASE_RUNBOOK §3).
+
+## Recommended settings, by use case
+
+Swept on the predecessor ifc-s50 container (`39787a2e…`); the sampling sweep was NOT re-run for `016c6f36…` across four prompt slices — chat,
+factual, structured/tool-shaped, long-form — at four temperature x
+repetition-penalty cells (`handoffs/results_recommended_configs`). `—` means
+leave it alone; a number there would be one we did not measure.
+
+| use case | temperature | top-p | top-k | repetition penalty | penalty window | max new tokens | stop |
+|---|---|---|---|---|---|---|---|
+| **conversation / assistant** | **0.01** on the C binary · **0** on torch | 1.0 | not exposed | 1.05 | 256 | **512** | EOS `151645` |
+| **tool calling / structured output** | **0** (greedy) | — | — | **1.0 (off)** | — | 256 | EOS `151645` |
+| **long-form prose** | **0.7** | 0.95 | not exposed | 1.05 | 256 | **1024** | EOS `151645` |
+| **deterministic / scriptable / benchmarks** | **0** (greedy) | — | — | **1.0 (off)** | — | 256 | EOS `151645` |
+
+- **Structured output is an 8B capability.** On tool-shaped prompts this
+  model emitted whole-reply, fence-free, parseable JSON **8/8 in every cell
+  tried, including at temperature 0.7** — the format is not sensitive to the
+  sampler here. Turn the repetition penalty **off** for it anyway: JSON
+  requires repeating `"`, `:` and `{`, and a penalty over that punctuation is
+  the one place it can actively break the format. The 0.6B-Chat scored 0/8 on
+  the same prompts at every setting; route schema-shaped work here.
+- **Why 512 and 1024 token budgets.** These are measured, not taste. At a
+  150-token cap the chat slice terminated 0/2 in every cell and every
+  long-form generation hit the cap. The 8B is verbose; give it room.
+- **The repetition penalty is insurance, not a fix.** Loop rate was **0.000
+  in all four cells**, with and without it. It is in the conversation row to
+  match what the behaviour receipts were graded at, and it is off everywhere
+  reproducibility matters.
+- **`top_p 0.95` on the long-form row is the one unmeasured number here** —
+  we swept top-p 1.0 only. It is the conventional pairing for temperature
+  0.7, flagged as convention rather than measurement.
+- **Top-k is not exposed on any runtime we ship**, and this repo's
+  `generation_config.json` sets none. Top-p is the only shortlist knob.
+- **`--stop-id 151645` is mandatory on the C binary.** Without it the binary
+  runs in fixed-length "race mode", ignores EOS and emits exactly the token
+  count you asked for.
+- **Speculative decoding and the exactness claim.** Token-identical output is
+  certified under **greedy** decoding (`--temperature 0`). With sampling,
+  drafted output is drawn from the same distribution as undrafted output —
+  the pip path routes through the transformers rejection-sampling correction
+  — but individual tokens will differ. The research CUDA engine and the MLX
+  `--spec` mode use argmax-match acceptance and are greedy-only.
+- Exactly one repetition penalty ever applies on the torch path: the
+  `fermion` CLI pins `repetition_penalty=1.0` in its `generate()` call before
+  installing its own windowed processor, so HF's full-context processor is
+  never built alongside it. If you assemble your own call, do the same — two
+  penalties of 1.05 compose to a measured 1.1025.
+
+## `bin/` — prebuilt native runtimes (the fast path)
+
+This repo bundles the prebuilt, closed-source `fermion-run` binaries next
+to the weights (the GGUF-ecosystem pattern; HF permits arbitrary binaries):
+
+| Binary | Platform | Backend |
+|---|---|---|
+| `bin/fermion-run-macos-arm64` | macOS arm64 (M1+) | CPU — NEON dotprod, zero dylib deps (Metal runtime is a week-one follow-up) |
+| `bin/fermion-run-linux-x64` | Linux x86-64 | CPU — AVX2 baseline, fully static ELF |
+| `bin/fermion-run-linux-cuda` | Linux x86-64 + NVIDIA | CUDA — **coming soon** (not yet staged; today's CUDA fallback is the pip torch path) |
+
+Every binary ships with a `<name>.sha256` sidecar; verify before running:
+
+```bash
+shasum -a 256 -c bin/fermion-run-macos-arm64.sha256
+```
+
+`pip install fermion` remains the one door: the CLI downloads the model and
+the platform-matching binary from THIS repo and shells out to it for the
+fast path (the torch reference path stays as the fallback). Until the
+auto-binary CLI lands, the documented one-command binary path is in
+`bin/README.md`.
+
+Shipped-binary speed, with venue: **24.94 tok/s** CPU-only on an M5
+MacBook (the macOS arm64 binary, 9 threads, 32-token greedy, banked
+2026-07-25) and **25.0 tok/s median** via the MLX pack on a 16 GB M5
+under a 6 GiB memory cap (`mlx/receipts/`). These are shipped-binary
+numbers; our research-harness results are reported separately and never
+conflated with them.
+
+Binaries are closed-source and covered by the EULA line below; speed
+receipts (venue+version+date on every number) live in the eval-receipts
+repo. `bin/MANIFEST.json` in this tree is the staging manifest: it names
+exactly which binaries land at upload time and their provenance.
+
+## Benchmarks
+
+Everything here is **non-thinking**: all our numbers, and every
+same-harness cell we publish for another model, are measured with
+thinking disabled. Release battery: the shipped brain (IF-stack
+snapshot-50 + verifiable-reward tool-calling dose-25, "d25"), graded
+2026-07-26 on our house harness; all five release guards (termination,
+IFEval floor, Redux, knowledge-delta, C4 ppl) plus the tool-calling
+primary and stretch targets passed before the container was baked
+(VERDICT PASS, `results_bfcl_round2/r2_summary.json`). A receipt exists
+for every cell (venue, version, date) in the eval-receipts repo.
+
+Release battery of the ship brain, protocol on every row:
+
+| Meter | Score | Protocol |
+|---|---:|---|
+| MMLU full-57 | 72.1 **[MMLU-adapted, disclosed — see banner]** | 5-shot likelihood, 14,042 items |
+| MMLU-Redux | 67.84 | generative, thinking off |
+| IFEval, prompt-strict | 73.17 | generative, thinking off |
+| IFEval, instruction-strict | 80.22 | same run, per-instruction grading |
+| IFEval, prompt-loose | 76.31 | same run, loose extraction |
+| BFCL v3 | 65.31 | macro over 13 subsets, bfcl-eval 2025.10.27.1, thinking off |
+| GSM8K, flexible-extract | 51.00 | 0-shot generative, greedy, 256-token cap |
+| GSM8K, strict/stated format | 49.33 | same run, answer must appear in the stated format |
+
+Same-harness reference points for the strongest same-byte-class open
+model (Ternary-Bonsai-8B, measured by us on identical protocols):
+MMLU 65.75 · MMLU-Redux 71.47 · IFEval prompt-strict 83.65 · BFCL v3
+71.45 · GSM8K flexible 35.00 · **GSM8K stated-format 39.67**. It leads us
+on instruction following, tool calling and MMLU-Redux; we lead on MMLU
+full-57, on GSM8K flexible extraction (51.00 vs 35.00) and — new with this
+brain — on **GSM8K stated-format extraction, 49.33 vs 39.67**, the one
+column the category leader previously held. (Its MMLU cell is
+clean-lineage; ours carries the adaptation banner.)
+
+### Reproducing the battery
+
+The model registers as a native `transformers` model (`import fermion`),
+so the public harnesses run directly. MMLU / GSM8K were graded with
+lm-eval:
+
+```python
+import fermion, lm_eval
+from lm_eval.models.huggingface import HFLM
+from transformers import AutoModelForCausalLM, AutoTokenizer
+
+model = AutoModelForCausalLM.from_pretrained("fermionresearch/Neutrino-8B")
+tok = AutoTokenizer.from_pretrained("fermionresearch/Neutrino-8B")
+lm = HFLM(pretrained=model, tokenizer=tok)
+lm_eval.simple_evaluate(model=lm, tasks=["mmlu"], num_fewshot=5)
+lm_eval.simple_evaluate(model=lm, tasks=["gsm8k"], num_fewshot=0)  # flexible-extract
+```
+
+IFEval, MMLU-Redux, and BFCL v3 were graded with evalscope 1.4.2 against
+a vLLM OpenAI-compatible endpoint serving this model, with
+`chat_template_kwargs: {"enable_thinking": false}` and
+`bfcl-eval==2025.10.27.1` pinned:
+
+```bash
+pip install evalscope==1.4.2 bfcl-eval==2025.10.27.1
+evalscope eval --model Neutrino-8B --api-url http://127.0.0.1:8000/v1 \
+    --datasets ifeval mmlu_redux bfcl_v3
+```
+
+The exact per-leg configs (context lengths 8k/16k, generation configs,
+the BFCL 13-subset list) and every raw report JSON are in the
+eval-receipts repo.
+
+| Meter | Neutrino-8B | Same-harness comparison | Receipt |
+|---|---:|---|---|
+| MMLU full-57 (5-shot likelihood, n=14,042) | **72.1** **[MMLU-adapted, disclosed — see banner; not comparable to clean models]** | Ternary-Bonsai-8B 65.75 · Gemma-4-E4B 70.57 (non-thinking) — both measured by us on the identical harness | eval-receipts repo, d25 grade (`full57_25/`) |
+| MMLU-CF (blind, contamination-free, val-10K) | 54.32 — the W-7500 brain this stack is trained from; the shipped snapshot's own CF cell is not yet measured (behavior stages moved full-57 by ≤0.2 pp, ns) | Ternary-Bonsai-8B 54.31 — dead even. Clean-lineage anchors: 52.74 / 53.61 | eval-receipts repo |
+| TruthfulQA mc1 / mc2 (0-shot likelihood) | 34.52 / 53.57 — clean-lineage anchor checkpoint (internal, not this SKU) | Ternary-Bonsai-8B 32.19 / 51.12 — both wins significant (paired McNemar, p=0.0448 / p=0.0079) | eval-receipts repo |
+| GSM8K flexible-extract (0-shot generative, greedy, 256-token cap, fixed 300-item subset) | **51.00** (shipped brain, cons3-B25) | Ternary-Bonsai-8B 35.0 on the byte-identical meter | eval-receipts repo |
+| GSM8K stated-format (same run, answer must land in the prescribed format; 1024-token cap) | **49.33** (shipped brain, cons3-B25; was 29.33 on ifc-s50) | Ternary-Bonsai-8B **39.67** on the byte-identical meter — this column is ours as of this brain | eval-receipts repo |
+| MMLU full-57 — clean-lineage calibration anchors (internal checkpoints, NOT products) | 63.43 (stage-B step-800) / 63.99 (decay-6.5K research branch) | — | eval-receipts repo |
+
+Don't-regress guards, held at release (guards, not headlines): GSM8K
+generative termination 0.51 — above the bf16 teacher's 0.42 anchor on the
+same raw-completion meter, but now BELOW the snapshot-50 stage base (0.63)
+and the pre-stack base (0.593); the consolidation stage traded termination
+rate for stated-format accuracy and we state that plainly — and C4
+perplexity 21.48 (ifc-s50 21.46, snapshot-50 21.47, base 21.40 — flat
+across every behavior stage). The
+raw-completion protocol suppresses EOS across model families, ours and
+fp16 alike; chat-templated serving terminates normally.
+
+The trained-on-public-MMLU disclosure travels with every 72.1-class number,
+here and in every table this model appears in. The clean-lineage rows are
+calibration anchors for the contamination-fingerprint method (gap =
+original MMLU minus blind MMLU-CF; clean band 10.4–10.7 pp, adapted band
+15.9–17.8 pp), published in full in the eval-receipts repo.
+
+Tool calling is a trained, measured capability of this brain, stated
+here as our own absolute numbers (no comparison rows on this axis):
+two stacked verifiable-reward stages built this brain. The
+tool-calling stage lifted BFCL v3 13-subset macro 42.15 → 62.60
+(bfcl-eval 2025.10.27.1, our harness, thinking off); the
+instruction-following stage on top took IFEval prompt-strict 67.51 →
+72.75 while BFCL rose again to 63.67 and MMLU-Redux to 70.65 — a
+validated upgrade on every measured axis, no guard traded (receipts:
+`results_bfcl_round2/r2_summary.json` + `results_ifeval_bump/` A1 walk).
+A third, **consolidation** stage then took IFEval prompt-strict to
+**73.17**, BFCL to **65.31** and GSM8K stated-format from 29.33 to
+**49.33** — and, unlike the first two, this one **did** trade a guard:
+MMLU-Redux fell to **67.84** and GSM8K flexible extraction to **51.00**.
+That trade was made deliberately and is disclosed here rather than
+buried (receipts: `results_consolidation_3/RESULTS.md`).
+Honest read: instruction-following and tool-calling absolutes are still
+below where we want them against the class, and instruction-following
+upgrades continue through week one; the numbers live — like everything
+else — in the eval-receipts repo.
+
+<!-- [SHIP-BRAIN RE-PIN 016c6f36… — publish gates] Card re-pinned from
+the ifc-s50 bake to the cons3-B25 ship brain (FOUNDER-AUTHORISED PROMOTE
+2026-07-27 ~19:50 IST over a deliberate MMLU-Redux guard amendment:
+GSM8K stated 49.33 / flexible 51.00 / BFCL 65.31 / IFEval-ps 73.17 /
+redux 67.84 / full57 72.084 / c4 21.475 / term 0.5067, receipts
+results_consolidation_3/RESULTS.md). CARRY-OVER GATES re-run against THIS
+container 2026-07-27: (1) pip acceptance rerun — NOT YET RUN, still
+outstanding; (2) MLX path+ref gate — DONE, both PASS; (3) GGUF re-cut +
+token-identity gate — DONE; (4) dspec cert — DONE, PASS 27,648 tokens
+0 mismatches.
+Each is a fan-out leg of the ship-brain bake; swap its receipt in and
+regenerate MANIFEST as it lands. -->
+
+## Weights: get them and verify them
+
+The container ships in this repository. Fetch it and check the digest —
+`MANIFEST.json` carries the same sha256, and `fermion info` verifies it for
+you automatically:
+
+```bash
+hf download fermionresearch/Neutrino-8B neutrino-8b_v4.bin --local-dir .
+shasum -a 256 neutrino-8b_v4.bin         # must print 016c6f362...b4155fa0
+```
+
+<!-- Retirement record (receipts culture; internal archive locations are not
+published). Superseded containers, by sha256:
+  fe85f9321...768b08d5 — earlier product bake, retired 2026-07-26.
+  be44129e5...81b814   — interim stage-B step-800 development container,
+                         retired earlier; carried the pre-launch working slug.
+Their acceptance/export receipts are held out of this published tree, in
+packaging/retired_receipts_not_published/, because this repo ships only
+016c6f362...b4155fa0 and provenance for a brain we do not ship is misleading.
+  39787a2e1...2007a3be — ifc-s50 ship brain, retired 2026-07-27 by the
+                         consolidation-3 arm-B-step-25 promote.
+-->
+
+Product bake provenance: exported on a Modal CPU container from the
+archived consolidation-3 arm-B dose-25 QAT state — the ship-brain
+lineage is IF-stack snapshot-50 → round-2 dose-25 verifiable-reward
+tool-calling (step-25 sha256 `752d01d5…3abbc`) → IF-checker stage dose-50,
+VALIDATED-BUMP (step-50 sha256 `e62a1199…0fb6a9`) → **consolidation-3
+arm B dose-25** (step-25 sha256 `09c3f36a…41b8`,
+32,768,963,587 bytes, banked 2026-07-27 11:40Z —
+`results_consolidation_3/RESULTS.md`) with the banked
+exporter (`export_trit_c_model.py`, pinned command + flags recorded in
+the export receipt; quantizer parameters are not published); full receipt at S3
+`archive/bfcl_round2/export_v4/export_receipts.json` (the in-tree
+`receipts/` acceptance + export copies are still the RETIRED s50 bake's —
+swap them, plus the fresh acceptance receipt, into `receipts/` and
+regenerate this tree's MANIFEST after the §3 acceptance rerun).
+<!-- RETIRED 2026-07-26 s50 provenance (kept per receipts culture): IF-stack
+snap50 QAT state sha256
+f31195a8e2fcdeff0c42b9e3968a8259d44e647e93f601d77d74b5980bffa2a2,
+32,768,963,587 bytes, durably archived at
+archive/if_stack_b800/snap50/last_state.pt; bake receipt
+archive/if_stack_b800/export_v4/export_receipts.json; exporter flags
+identical. Earlier retirement (interim): QAT state sha256
+a1ffcf409c0330345e240397093f61654ad013ed8935a62a0a19164d99daa1f9,
+32,768,963,587 bytes; exporter flags identical. -->
+
+## Runtime matrix
+
+Single-stream decode, one artifact across every row (venue + date on each
+number in the eval-receipts repo):
+
+| Platform | Surface | Rate | Memory |
+|---|---|---:|---|
+| H100 80 GB | research stack, drafted (0.6B draft, certified exact) | 763 tok/s (counting; 402-500 tok/s on other prompt classes) | — |
+| H100 80 GB | research stack, plain greedy | 396 tok/s | — |
+| NVIDIA L4 | GGUF pack via our CUDA fork, full offload | 30.7 tok/s | 4.68 GiB @ 4k ctx |
+| Apple M5, 16 GB | MLX pack (median, 3 runs) | 25.0 tok/s | 3.67 GiB peak, 6 GiB cap |
+| Apple M5 | `bin/` native binary, CPU only, 9 threads | 24.94 tok/s | < 8 GiB resident |
+
+## Speculative decoding (certified exact)
+
+This repo's 8B pairs with [Neutrino-0.6B-Chat](https://huggingface.co/fermionresearch/Neutrino-0.6B-Chat)
+as a **draft model** for speculative decoding: the 0.6B proposes tokens,
+the 8B verifies them, and the output is **token-identical to plain 8B
+greedy decode** — speculation changes throughput, never the answer. Both
+models are the same TRTC v4 container format and run on the same
+`fermion-run` binaries, so the pairing needs no extra conversion.
+
+| Meter | Value | Note |
+|---|---:|---|
+| Certification (exact-match tokens) | **27,648 spec tokens, 0 mismatches** (receipt `receipts/dspec_cert_cons3_b25.json`, re-run against THIS container 2026-07-27; 54/54 arm x prompt cells identical) | draft+verify vs plain greedy, N tokens, 0 mismatches required |
+| Counting-style prompts | **×1.92 (763 tok/s vs 397 plain)** | measured speedup vs plain 8B greedy |
+| Factual / short-answer prompts | **×1.26 (500 tok/s)** | " |
+| Code | ×1.10 (437 tok/s) | " |
+| Prose continuation | ×1.06 (422 tok/s) | " |
+| Conversational explanation | ×1.01 (402 tok/s) | " |
+| Venue | H100, 3-round median, dynamic-k controller, 2026-07-27 | same-moment, same-machine protocol (see VERIFY) |
+
+Mechanics (measured on this brain, 2026-07-27 cert run): on counting
+prompts the 8B still accepts 100% of drafted tokens; on factual prompts
+acceptance is 86.9% and on chat-factual 90.3%; it falls to 81.4% on prose
+and 50.0% on technical explanation. Acceptance decays with draft length
+everywhere except counting, so the dynamic-k controller shortens its
+drafts there and the gain thins. **This brain drafts less well than
+ifc-s50 did** on everything but counting — the speedup table above is
+lower across four of five rows, and that is a throughput regression we
+state rather than carry over the old numbers.
+
+Receipts: `receipts/dspec_cert_cons3_b25.json` (banked, ship brain).
+Honest framing: speculative decoding is a **throughput** feature with a
+correctness certificate; it does not change quality, and the speedup is
+prompt-dependent — the five rows above are the honest spread, not a
+single headline number.
+
+## Limitations
+
+- Chat-tuned for short helpful answers. Tool calling is trained and
+  measured (BFCL v3 13-subset macro 65.31, our harness — see Benchmarks)
+  but carries no guarantees at this size; instruction-following and
+  tool-calling absolutes are below where we want them against the class,
+  and instruction-following upgrades continue through week one.
+- This is a non-thinking model: it ships and is evaluated with thinking
+  disabled (`enable_thinking=False`).
+- MMLU-family numbers carry the [MMLU-adapted, disclosed] label by
+  construction — never quote this model's 72.1-class cells without it.
+  The blind MMLU-CF cell and the clean-lineage anchors are the honest
+  cross-model meters.
+- Against the strongest same-byte-class open model on identical
+  protocols, instruction following and tool calling trail: their 83.65
+  IFEval prompt-strict and 71.45 BFCL v3 vs our 73.17 and 65.31. Their
+  MMLU-Redux 71.47 also leads our 67.84.
+- GSM8K stated-format and flexible extraction now sit close together
+  (49.33 vs 51.00, same run): the format gap that used to be 33 points is
+  largely closed. The cost, disclosed above, is that flexible extraction
+  itself fell from 62.67, so the model lands the prescribed format far
+  more reliably but solves slightly fewer problems overall.
+- The GGUF pack loads only through our llama.cpp fork (`gguf/`) until
+  upstreaming lands; stock llama.cpp, ollama, and LM Studio binaries do
+  not know the FV5/FV5B tensor types.
+- The pip package's torch path prioritizes bit-exactness over throughput;
+  use the `bin/` runtimes in this repo for speed.
+- The family's chat 0.6B SKU is not bit-identical across its three
+  shipping runtimes (near-tie argmax flips at small logit margins; each
+  runtime deterministic on its own) — see the Neutrino-0.6B-Chat card.
+- Knowledge cutoff and multilingual behavior inherit from the Qwen3-8B base
+  plus our disclosed post-training mix; see the data disclosure in
+  eval-receipts.
+
+## Model lineage and methodology
+
+The full methodology — the ternary QAT recipe, the staged post-training
+program (combined behavior stage → IF-1 instruction stack → two
+verifiable-reward stages), the contamination-fingerprint method behind
+the MMLU banner, and the per-cell receipts (venue, version, date) — is
+published in the eval-receipts repo. The engineering story of the format
+and the engine is on the research pages at fermionresearch.com/research/.
+Lineage in one line: base model (see frontmatter) → ternary QAT →
+MMLU-adapted W-7500 brain (disclosed) → combined behavior stage → IF-1
+stack snapshot-50 → verifiable-reward tool-calling dose-25 → IF-checker
+dose-50, baked 2026-07-26 as the ship container pinned above.
+
+## License and attribution
+
+Weights: Apache-2.0. Derivative of Qwen/Qwen3-8B (Apache-2.0, Alibaba
+Cloud) — see `LICENSE`. Post-training data sources are disclosed in the
+eval-receipts repo (UltraChat, MetaMath, the public `cais/mmlu` splits per
+the banner, and the other accepted-source datasets).
+
+`bin/` binaries: prebuilt, closed-source, free to use with these weights;
+no redistribution outside this repo; no reverse engineering. [EULA short
+text — final wording lands with the binaries at upload; RELEASE_RUNBOOK §6.]
+
+Contact: [PENDING-DNS: mailbox on fermionresearch.com — fill when mail is configured]

bin/MANIFEST.json

@@ -0,0 +1,25 @@
+{
+ "note": "bin/ staging manifest: blessed fermion-run release binaries (release-binaries lane, 2026-07-25; receipts in handoffs/results_release_binaries/). Entries mirror the .sha256 sidecars. Functional gates ran against the INTERIM dev container (bake sha256 be44129e...); rerun the one-command smoke after the final W-pipeline product bake lands (RELEASE_RUNBOOK par.4) \u2014 the binaries are container-agnostic (any TRTC v4 arch-3 file) so no rebuild is expected.",
+ "binaries": {
+  "fermion-run-macos-arm64": {
+   "status": "RE-BLESSED 2026-07-27 (thread-safety rebuild, results_native_threadfix): macOS arm64 CPU runtime (NEON dotprod + persistent thread pool; libomp statically linked, only libSystem dep). Supersedes the 2026-07-25 build b963de1a..., which overflowed the per-thread activation-quant buffer above 16 threads. Gated by an OUTPUT-STABILITY thread sweep (packaging/acceptance/thread_sweep.py): byte-identical generated ids at 1/4/8/15/16/17/20/23/max threads on the 0.6B and the 8B, and identical to the superseded binary's output at every thread count it survived.",
+   "bytes": 621480,
+   "sha256": "d7b257b5cd4b08cadd04fd867158ac50619aab23164294794dc10f05f1ede53c",
+   "sidecar": "fermion-run-macos-arm64.sha256",
+   "build_receipt": "handoffs/results_release_binaries/receipt_macos_arm64.json"
+  },
+  "fermion-run-linux-x64": {
+   "status": "RE-BLESSED 2026-07-27 (thread-safety rebuild, results_native_threadfix): Linux x86-64 CPU runtime, AVX2 baseline (-march=x86-64-v3), fully static ELF, same source and flags as the 2026-07-25 build. Supersedes 4a09b5cb..., which SIGSEGVed on the 8B and returned silently WRONG TOKENS at exit code 0 on the 0.6B above 16 threads. Gated by the same output-stability thread sweep, run on a 24-core Linux venue.",
+   "bytes": 1249584,
+   "sha256": "499ecdc569eae2ceaeb4a34cd1f11a91c2c09dfb17aa5847532359c6dc57d93a",
+   "sidecar": "fermion-run-linux-x64.sha256",
+   "build_receipt": "handoffs/results_release_binaries/receipt_linux_x64.json"
+  },
+  "fermion-run-linux-cuda": {
+   "status": "COMING-SOON (NOT STAGED, no fake artifact): no arch-3 (Qwen3) CUDA runtime exists in kernels/gpu_e2e/ (arch-1/arch-2 walkers only) and the CUDA lane was Python+torch-extension harnesses, never a standalone binary. Blocker + week-one lane recommendation: handoffs/results_release_binaries/CUDA_BLOCKER.md. Working fallback documented in bin/README.md: pip fermion torch path with --device cuda.",
+   "bytes": null,
+   "sha256": null,
+   "sidecar": null
+  }
+ }
+}

bin/README.md

@@ -0,0 +1,140 @@
+# bin/ — prebuilt `fermion-run` native runtimes
+
+STATUS: **BLESSED BINARIES STAGED 2026-07-25** (release-binaries lane;
+receipts in `handoffs/results_release_binaries/` in the research tree).
+Binaries are prebuilt and closed-source (kernel source does not ship);
+every binary has a `.sha256` sidecar. EULA line lives on the model card.
+Functional gates ran on the interim 8B v4 cut; the runtime is
+container-agnostic (any TRTC v4 arch-3), and the RELEASE_RUNBOOK §3
+acceptance rerun against the final product container (`016c6f36…`, the
+cons3-B25 ship brain — supersedes ifc-s50 `39787a2e…` and d25
+`06af07b5…`) is a publish gate and is STILL OUTSTANDING.
+
+## What is here
+
+| File | Platform / backend | State |
+|---|---|---|
+| `fermion-run-macos-arm64` | macOS arm64 (M1+), CPU — NEON dotprod + persistent thread pool, OpenMP statically linked, zero dylib deps beyond libSystem | BLESSED (functional-gated on the 8B v4 container) |
+| `fermion-run-linux-x64` | Linux x86-64, CPU — AVX2 baseline (`-march=x86-64-v3`), fully static ELF, runs on any 2015+ x86-64 distro | BLESSED (functional-gated on the 8B v4 container) |
+| `fermion-run-linux-cuda` | Linux x86-64, NVIDIA CUDA | **COMING SOON** — not staged; see fallback below |
+
+Honesty notes, so nobody is surprised:
+
+- The macOS binary is the **CPU** runtime. The Metal-optimized runtime for
+  this model's container format is a week-one follow-up (the existing Metal
+  dev builds target a different container lineage and cannot load this
+  model); when it lands it replaces this entry with its own receipts.
+- The linux-x64 binary is built for the AVX2 **compatibility baseline**, not
+  the AVX-512-VNNI fast path the banked x86 speed receipts were measured on.
+  It is correct (bit-exact GEMV unit gate at build time) and self-contained;
+  a VNNI-optimized variant is a week-one candidate.
+- CUDA fallback that works today: `pip install fermion` then
+  `fermion chat --model fermionresearch/Neutrino-8B --device cuda`
+  (reference torch path — correctness-first, not the speed path).
+
+## CLI (what the binaries actually take)
+
+The binaries take **pre-tokenized ids**, not prompt strings — tokenization
+lives in the `fermion` CLI (`pip install fermion`, the one door), which
+downloads the model + the platform-matching binary from this repo and shells
+out for the fast path. Manual use:
+
+```
+./fermion-run-<platform> <container.bin> "<id0,id1,...>" <n_new_tokens> <n_threads> \
+    [logits_out.bin] [--temp T] [--top-p P] [--rep-pen R] [--seed S] \
+    [--stop-id I0[,I1...]] [--min-p F] [--presence-pen F] [--freq-pen F] \
+    [--dry MULT [--dry-base B --dry-allow N]] [--pen-window N] \
+    [--eos-exempt-minp] [--eos-boost B:N] [--ppl]
+```
+
+The container, the id list, the token count and the **thread count are
+positionals, in that order**. There is no `--chat` and no `--threads`.
+
+> [!IMPORTANT]
+> **Sampler flags require `--temp > 0` to engage.** At `--temp 0`
+> (pure greedy) the binary takes a fast argmax path and silently
+> ignores `--rep-pen`, `--top-p`, and all other penalty flags. If
+> you want penalties with near-deterministic output, use
+> `--temp 0.01 --top-p 1.0 --seed 42`. (Found 2026-07-26; a
+> runtime patch making this explicit is a week-one item.)
+>
+> **`--pen-window` is inert on the legacy sampled path.** With `--temp > 0`
+> and none of `--min-p` / `--presence-pen` / `--freq-pen` / `--dry` present,
+> the repetition-penalty window is clamped to the last **64** tokens
+> regardless of what `--pen-window` says (`trit_run.c`: `rwin = g_ext ?
+> max(g_penwin, 64) : 64`). Adding any one of those four flags switches on
+> the modern penalty stack and makes `--pen-window` literal. Every graded
+> C receipt was taken on the legacy path, so the banked C numbers are
+> **64-window** numbers even where the command line reads
+> `--pen-window 256`; the torch and MLX paths do apply 256. Documented
+> 2026-07-27 (results_pip_native + results_0p6b_binaries); making the flag
+> literal on the legacy path is a week-one runtime patch.
+
+Defaults: greedy decode; without `--stop-id` exactly `n_new_tokens` are
+generated (EOS ignored); with `--stop-id` generation stops at the stop token
+(coherence mode). Output: line 1 = generated ids (comma-separated), line 2 =
+`tok/s: ...`. `n_new_tokens 0` = prefill-only logits dump.
+
+Per-platform one-liners (chat-format ids for a user prompt, then generate up
+to 64 tokens, stop at `<|im_end|>` = 151645):
+
+```bash
+# ids for 'In one sentence, why is the sky blue?' via this repo's tokenizer:
+IDS=$(python3 -c "
+from tokenizers import Tokenizer
+t = Tokenizer.from_file('tokenizer.json')
+p = '<|im_start|>user\nIn one sentence, why is the sky blue?<|im_end|>\n<|im_start|>assistant\n<think>\n\n</think>\n\n'
+print(','.join(map(str, t.encode(p).ids)))")
+
+# macOS arm64:
+./bin/fermion-run-macos-arm64 neutrino-8b_v4.bin "$IDS" 64 8 --stop-id 151645
+# Linux x86-64:
+./bin/fermion-run-linux-x64 neutrino-8b_v4.bin "$IDS" 64 8 --stop-id 151645
+```
+
+macOS quarantine note: after download run
+`xattr -d com.apple.quarantine bin/fermion-run-macos-arm64` once.
+
+## sha256 sidecar convention
+
+Every binary `X` ships with `X.sha256` (standard `shasum` line):
+
+```bash
+# producer (at staging time, from this directory):
+shasum -a 256 fermion-run-macos-arm64 > fermion-run-macos-arm64.sha256
+# consumer:
+shasum -a 256 -c fermion-run-macos-arm64.sha256
+```
+
+`MANIFEST.json` here mirrors the sidecars (file -> bytes + sha256 + build
+provenance) and is regenerated by `packaging/receipts/gen_manifests.py`
+whenever binaries are added or replaced.
+
+## Upload checklist (mirrors RELEASE_RUNBOOK §6)
+
+1. Binaries + sidecars staged here (done 2026-07-25, receipts in the lane).
+2. Regenerate the tree MANIFEST (`packaging/receipts/gen_manifests.py`).
+3. After `hf upload`, re-download each binary and `shasum -a 256 -c` its
+   sidecar (the §6 re-download hash-verify rule applies to binaries too).
+4. One-command smoke on a machine matching each platform before flipping
+   the repo public (macOS leg locally is fine — the C runtime is not the
+   8B torch load, but respect the RSS budget; linux leg on Modal).
+
+## thread count: the runtime is safe above 16 threads again
+
+> [!IMPORTANT]
+> **Rebuilt 2026-07-27 (thread-safety fix).** The 2026-07-25 binaries
+> corrupted memory above **16 threads**: the per-thread activation-quant
+> scratch buffer inside the runtime was allocated for 16 workers while the
+> OpenMP path indexed it by thread id with no clamp. On Linux x86-64 that was
+> a SIGSEGV on the 8B and — worse — **exit code 0 with silently different,
+> wrong tokens** on the 0.6B, on any box with 18 or more logical cores (the
+> `fermion` CLI asked for `cpu_count - 1`). macOS arm64 never reached it
+> because Apple silicon tops out at 16 logical cores.
+>
+> These binaries size that buffer from the live thread count, clamp the
+> requested count at a hard ceiling, and are gated by an output-stability
+> thread sweep (`packaging/acceptance/thread_sweep.py`) that asserts
+> **byte-identical generated ids** at 1/4/8/15/16/17/20/23/max threads rather
+> than merely a zero exit code. The `fermion` package independently caps the
+> count it will request at 16 (`fermion.native.THREAD_CAP`).

bin/fermion-run-linux-x64

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:499ecdc569eae2ceaeb4a34cd1f11a91c2c09dfb17aa5847532359c6dc57d93a
+size 1249584

bin/fermion-run-linux-x64.sha256

@@ -0,0 +1 @@
+499ecdc569eae2ceaeb4a34cd1f11a91c2c09dfb17aa5847532359c6dc57d93a  fermion-run-linux-x64

bin/fermion-run-macos-arm64

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:d7b257b5cd4b08cadd04fd867158ac50619aab23164294794dc10f05f1ede53c
+size 621480

bin/fermion-run-macos-arm64.sha256

@@ -0,0 +1 @@
+d7b257b5cd4b08cadd04fd867158ac50619aab23164294794dc10f05f1ede53c  fermion-run-macos-arm64

config.json

@@ -0,0 +1,24 @@
+{
+  "transformers_version": "5.14.1",
+  "architectures": null,
+  "output_hidden_states": false,
+  "return_dict": true,
+  "dtype": "auto",
+  "chunk_size_feed_forward": 0,
+  "is_encoder_decoder": false,
+  "id2label": {
+    "0": "LABEL_0",
+    "1": "LABEL_1"
+  },
+  "label2id": {
+    "LABEL_0": 0,
+    "LABEL_1": 1
+  },
+  "problem_type": null,
+  "_name_or_path": "",
+  "container": "neutrino-8b_v4.bin",
+  "row_chunk": 512,
+  "int8_row_chunk": 4096,
+  "model_type": "trtc_v4",
+  "output_attentions": false
+}

generation_config.json

@@ -0,0 +1,10 @@
+{
+    "bos_token_id": 151643,
+    "do_sample": false,
+    "eos_token_id": [
+        151645,
+        151643
+    ],
+    "pad_token_id": 151643,
+    "transformers_version": "4.53.2"
+}

gguf/Modelfile

@@ -0,0 +1,5 @@
+# Neutrino-8B — ollama Modelfile (requires ollama built against the
+# fermion-fv5 llama.cpp fork; stock ollama cannot load the FV5 type)
+FROM ./neutrino-8b-fv5.gguf
+PARAMETER temperature 0.7
+PARAMETER top_p 0.95

gguf/README.md

@@ -0,0 +1,223 @@
+# Neutrino-8B — GGUF pack (llama.cpp fork `fermion-fv5`)
+
+Run [Neutrino-8B](../README.md) through the **llama.cpp toolchain**
+(llama-cli, llama-server, llama-bench, and anything built on them,
+including ollama built from source against the fork).
+
+**Read this first — which door do you want?**
+
+- **This GGUF pack is the compatibility door.** It exists so the
+  llama.cpp/ollama/LM Studio world can load and run our format with the
+  ecosystem's own tooling. It runs on **CPU and CUDA** (full GPU offload
+  works — see below), is correctness-certified on both backends, and is
+  *not* tuned for peak speed.
+- **The native binaries are the fast door.** The `fermion-run` CPU
+  runtimes in this repo's `bin/` decode the same container at native
+  speed (see `bin/README.md`). If you want speed, use those; if you want
+  llama.cpp-ecosystem integration, use this pack.
+
+**Backend support, stated precisely:**
+
+| backend | status |
+|---|---|
+| CPU (x86-64 AVX2, Apple arm64) | shipped, certified |
+| **CUDA, full offload (`-ngl 99`)** | **shipped, certified** — measured below |
+| Metal | **not implemented** — no FV5 kernel; build Metal-off and run on CPU |
+| Vulkan / ROCm / SYCL | not implemented |
+
+> [!NOTE]
+> The digests in `SHA256SUMS` certify the **release product cut**:
+> converted and bit-checked (token-identical gate PASS, 2026-07-27 —
+> 8/8 free-running streams identical, 0/1024 teacher-forced mismatches,
+> 0 near-tie flips) from the release container `neutrino-8b_v4.bin`
+> (sha256 `016c6f36…55fa0`, the cons3-B25 ship brain — see the parent
+> card). Receipts in `receipts/`. Earlier cuts that certified this
+> pipeline (ifc-s50, d25, s50, W-baseline) are retired and commented in
+> `SHA256SUMS`; the ifc-s50 gate receipts are kept in
+> `receipts_ifcs50_retired/` as historical record.
+
+## What's in the file
+
+`neutrino-8b-fv5.gguf` stores the model in two Fermion GGML types added by
+the fork (they do **not** exist in stock llama.cpp):
+
+| type | used for | layout per 256-element block | bits/weight |
+|---|---|---|---|
+| `FV5` (43) | all 252 transformer linears | f32 `s_lo`, f32 `s_hi`, 3×32B bit-planes (`bp`,`bn`,`br`) | 3.25 |
+| `FV5B` (44) | int8 embedding + lm_head rows (untied) | f32 row scale, 256×int8 | 8.125 |
+
+Weights are `w = (bp − bn) · (br ? s_hi : s_lo)` — the exact five-value
+{0, ±s_lo, ±s_hi} function of the TRTC v4 container. The converter copies
+the container's bit-planes and f32 per-row dual scales verbatim (no
+re-quantization anywhere), and bit-compares every tensor's dequantization
+against the container's f32 expansion before writing. Norms stay f32.
+Activations are never quantized at runtime (`vec_dot_type = F32`), so the
+only numerical difference vs the fp32 expansion is float summation order.
+
+## Files
+
+See `SHA256SUMS` in this folder for the authoritative digests of:
+
+- `neutrino-8b-fv5.gguf` — the model (FV5/FV5B, ~4.2 GiB)
+- `fv5.patch` / `fermion-fv5.bundle` — the fork as a single patch/bundle
+  on top of upstream `ggml-org/llama.cpp` @ `d67c0b41`, branch
+  `fermion-fv5`, commit `e07b3ec1`, docs in `FORK_NOTES.md`
+
+## Quickstart (build the fork, run the model)
+
+```bash
+git clone https://github.com/fermionresearch/llama.cpp && cd llama.cpp
+git checkout fermion-fv5
+# or, from upstream + our patch:
+#   git clone https://github.com/ggml-org/llama.cpp && cd llama.cpp
+#   git checkout d67c0b4107112e4790774c3a8169e2e3eb24643b && git am fv5.patch
+
+# CPU
+cmake -B build -DCMAKE_BUILD_TYPE=Release -DLLAMA_CURL=OFF
+cmake --build build -j --target llama-completion llama-bench
+
+./build/bin/llama-completion -m neutrino-8b-fv5.gguf \
+    -p "Explain why the sky is blue." -n 256 --temp 0 -no-cnv
+```
+
+### CUDA (full offload)
+
+```bash
+cmake -B build -DCMAKE_BUILD_TYPE=Release -DLLAMA_CURL=OFF \
+      -DGGML_CUDA=ON -DGGML_CUDA_NO_VMM=ON -DCMAKE_CUDA_ARCHITECTURES=75\;89
+cmake --build build -j --target llama-completion llama-bench
+
+./build/bin/llama-completion -m neutrino-8b-fv5.gguf -ngl 99 \
+    -p "Explain why the sky is blue." -n 256 --temp 0 -no-cnv
+```
+
+`-DGGML_CUDA_NO_VMM=ON` is **required** when building on a box that has the
+CUDA toolkit but no driver (GPU-less builder/CI): without it the link fails
+on `cuGetErrorString` from the driver API. Drop it if you build on a machine
+with a real driver.
+
+**Measured, NVIDIA L4 (driver 580.95.05, 23 GB), full offload:**
+
+| metric | value |
+|---|---|
+| tg128 (decode) | **30.68 ± 0.05 tok/s** |
+| pp512 (prefill) | **477.1 ± 4.9 tok/s** |
+| VRAM peak @ 4096 ctx | **4680 MiB (4.68 GiB)** |
+
+An 8B model doing 30.7 tok/s inside 4.68 GiB of VRAM is the point of the
+format: this fits on a card that cannot hold an 8B at fp16 at all.
+
+> **`llama-server` is not in the verified target set.** The gated build ran
+> `-DLLAMA_BUILD_SERVER=OFF`, so we have not exercised the server against an
+> FV5 pack. It should work, but we will not print a command we never ran.
+> `llama-cli` likewise was not the gated target — `llama-completion` was.
+
+### ollama (built against the fork)
+
+Stock ollama binaries do not know the FV5 type. Build ollama from source
+with its vendored llama.cpp replaced by the fork checkout, then:
+
+```
+# Modelfile -- the conversation row of the parent card's recommended
+# settings. llama.cpp defaults would otherwise give you top-k 40 and a
+# 64-token penalty window, neither of which we measured.
+FROM ./neutrino-8b-fv5.gguf
+PARAMETER temperature 0
+PARAMETER top_p 1.0
+PARAMETER top_k 0
+PARAMETER repeat_penalty 1.05
+PARAMETER repeat_last_n 256
+PARAMETER num_predict 512
+PARAMETER stop "<|im_end|>"
+```
+
+For tool calling and JSON, drop the penalty (`PARAMETER repeat_penalty 1.0`):
+structured output measured 8/8 valid at every setting tried, and a penalty
+over `"`, `:` and `{` is the one thing that can break the format. For
+long-form prose, `temperature 0.7`, `top_p 0.95`, `num_predict 1024`.
+
+```bash
+ollama create neutrino-8b -f Modelfile
+ollama run neutrino-8b "Explain why the sky is blue."
+```
+
+LM Studio: point it at a llama.cpp server built from the fork
+(`llama-server -m neutrino-8b-fv5.gguf`) and connect via the
+OpenAI-compatible endpoint; the bundled engine cannot load FV5 directly.
+
+## Speculative decoding quickstart (llama.cpp native, EXPERIMENTAL)
+
+The fork inherits mainline llama.cpp's built-in speculative decoding, so
+the 0.6B fv5 pack can draft for this 8B out of the box. **Honesty note,
+read first**: the acceptance rule here is llama.cpp's own sampling-based
+speculation — **not** our bit-gated certification. This is "llama.cpp's
+native speculation with our models"; speeds vary by text; our
+certified-exact speculation lives in the native runtime (and the MLX pack's
+exactness-gated `--spec` mode).
+
+```bash
+cmake --build build -j --target llama-speculative
+./build/bin/llama-speculative -m neutrino-8b-fv5.gguf \
+    -md neutrino-0.6b-base-fv5.gguf \
+    -p "The three laws of thermodynamics state that" \
+    -n 128 --temp 0 -t 16 -td 16 --spec-draft-n-max 4
+```
+
+Note the flag surface: this tree removed `--draft-max` (use
+`--spec-draft-n-max`; the old flag errors out with a pointer).
+
+Measured on a Modal CPU container (16 threads, x86-64-v3 portable build,
+128-token greedy, 8B-wbase target + 0.6B-base draft;
+`receipts/gguf_spec_*.json`): **CPU speculative decode is currently a
+honest null for this pack — it is slower than plain decode at every draft
+depth we tried** (draft depth 16: 0.14–0.29× baseline; depth 4: 0.44–0.66× with
+llama.cpp-rule acceptance 30–57% — facts 5.3→3.5, code 5.4→3.1, prose
+5.4→2.4 tok/s on that host). Why: the FV5 ggml type has a fast `vec_dot` but no
+batched-matmul (sgemm) path yet, so verifying M draft positions costs
+almost M× a single token (~121 ms/position vs ~151 ms single-token in the
+perf prints) — the amortization that makes speculation win never happens,
+and per-token draft acceptance (llama.cpp's rule) of the base 0.6B for the
+8B is text-dependent on top. An FV5 sgemm path is the wired follow-up that
+would flip this; until then, plain `llama-completion`/`llama-cli` is the
+right way to run this pack on CPU.
+
+## Correctness & speed
+
+- **CPU gate:** greedy streams (8 prompts × 128 tokens) from the fork's CPU
+  backend, checked token-by-token against the container's fp32 expansion
+  reference. Verdict and near-tie argmax notes: `receipts/` in this folder.
+- **CUDA gate:** greedy streams (8 prompts × 256 tokens, `-ngl 99`,
+  `NVIDIA_TF32_OVERRIDE=0`) checked against the certified CPU path.
+  **7 of 8 prompts free-run token-identical; 2047 of 2048 teacher-forced
+  steps agree.** The single flip is a documented near-tie — step 0 of one
+  prompt, logits 15.631217 vs 15.630566, margin **6.5e-4**, inside the
+  preregistered 1e-3 bar — i.e. fp32 summation-order noise, not a kernel
+  defect. Zero unexplained flips. We report this rather than rounding it to
+  "identical"; the raw receipt is the authority.
+- **Speed:** CUDA numbers are in the table above. For CPU tok/s see
+  `receipts/bench_*.json`. The native runtime is still the fast door;
+  upstreaming and a SIMD-fused NEON `vec_dot` are wired follow-ups. Note the
+  speculative-decoding null documented above — do not assume it helps here.
+
+### Platform scope of the native binaries (`../bin/`)
+
+Two prebuilt runtimes ship: **macOS arm64** (NEON, static libomp) and
+**Linux x86-64**. They are not equivalent. The Linux binary is built to a
+portable **AVX2 baseline** so it runs on older hosts, which means it leaves
+AVX-512/VNNI performance on the table. **Apple-silicon throughput figures
+quoted elsewhere in this repo are Apple-silicon figures and do not transfer
+to the Linux x86-64 binary.** Both binaries verify against their `.sha256`
+sidecars in `../bin/`; on macOS and Linux you may need `chmod +x` after
+download, as the executable bit does not always survive transport.
+
+## License
+
+**This folder is mixed-licence. Read the split before you reuse anything.**
+
+- The **model pack** `neutrino-8b-fv5.gguf` is Apache-2.0, same as the
+  parent model card (`../LICENSE`, and `../NOTICE` for the Qwen3
+  attribution).
+- The **`fv5.patch` / `fermion-fv5.bundle` source** is a derivative of
+  ggml-org/llama.cpp and is therefore **MIT**, upstream's licence — *not*
+  Apache-2.0. It is not covered by the parent card's grant. See the fork
+  repository's own `LICENSE`.

gguf/SHA256SUMS

@@ -0,0 +1,23 @@
+# Neutrino-8B GGUF pack — authoritative digests (lane results_gguf_fork)
+# NOTE: this certifies the cons3-B25 SHIP-BRAIN cut (source container
+# neutrino-8b_v4.bin, sha256 016c6f36…55fa0), gate_fv5 PASS
+# token-identical 2026-07-27: verdict PASS, 8/8 free-running streams
+# identical, 0/1024 teacher-forced mismatches, 0 near-tie flips
+# (receipts/gateverdict_8b_fv5.json). Lane artifact name
+# neutrino-8b-cons3b25-fv5.gguf (S3 archive/labarchive/gguf_fork/gguf/ +
+# Modal volume ternary-gguf-fork-20260725); published here under the
+# plain name — byte-identical, digest below is the file's sha either
+# way. Verify with `shasum -a 256 -c`.
+1c13a34360b2531d28821fb6aee41708f99a040215a2522af37213c6c8c87211  neutrino-8b-fv5.gguf
+81bf7be5eef18eb98ab4823596374c8dd6615151cf5615425973cb65942c0f73  fv5.patch
+# source container: 016c6f362ad237a8cf4043601efbc1e766574f76ea58691e78fdef51b4155fa0  neutrino-8b_v4.bin
+# f32 control (not published): 089466ea7a8378b658a4ed0e24788bf67f6a81879d93dfa87a3e6863626d0532  neutrino-8b-cons3b25-f32.gguf
+# fork: ggml-org/llama.cpp @ d67c0b41 + fv5.patch = branch fermion-fv5, commit e07b3ec1 (tree f3067d90)
+# fermion-fv5.bundle sha256: 4fad510f32c9df84efda6a63dcb6de7d33f01590947111fdd337d17d2baf87e0
+# RETIRED cuts — do NOT verify against (pipeline certification lineage):
+# 7dda995047dc70540d2d83f2c464dd118fff62eef1aab36ae71ceb3cc972e5d0  neutrino-8b-ifc50-fv5.gguf (07-26 PM; retired 2026-07-27 by the cons3-B25 promote)
+# ae26b97fb17cdb843a34260b748f43dddc4ca3bb66321a2441e52ba2d5f5d687  neutrino-8b-d25-fv5.gguf (07-26 PM)
+# 210195d72d7858698a94e6aca8365c61648322112d4d3ee31ae1f1d36f730d29  neutrino-8b-s50-fv5.gguf (07-26 AM)
+# c4e82e295ad827918e205f46e6c6c874979321e6aac9f0d296b8175168e12861  neutrino-8b-wbase-fv5.gguf (07-25)
+# The ifc-s50 gate receipts are preserved beside this file in
+# receipts_ifcs50_retired/ (historical record; not the shipping gate).

gguf/receipts/bench_8b.json

@@ -0,0 +1,112 @@
+{
+ "model": "8b",
+ "bench": [
+  {
+   "build_commit": "e07b3ec",
+   "build_number": 2,
+   "cpu_info": "unknown",
+   "gpu_info": "",
+   "backends": "CPU",
+   "model_filename": "/vol/gguf/neutrino-8b-cons3b25-fv5.gguf",
+   "model_type": "qwen3 8B FV5 - 3.25 bpw Fermion five-value ternary",
+   "model_size": 4087058432,
+   "model_n_params": 8190735360,
+   "n_batch": 2048,
+   "n_ubatch": 512,
+   "n_threads": 16,
+   "cpu_mask": "0x0",
+   "cpu_strict": false,
+   "poll": 50,
+   "type_k": "f16",
+   "type_v": "f16",
+   "n_gpu_layers": -1,
+   "n_cpu_moe": 0,
+   "split_mode": "layer",
+   "main_gpu": 0,
+   "no_kv_offload": false,
+   "flash_attn": -1,
+   "devices": "auto",
+   "tensor_split": "0.00",
+   "tensor_buft_overrides": "none",
+   "load_mode": "mmap",
+   "embeddings": false,
+   "no_op_offload": 0,
+   "no_host": false,
+   "fit_target": 0,
+   "fit_min_ctx": 0,
+   "n_prompt": 512,
+   "n_gen": 0,
+   "n_depth": 0,
+   "test_time": "2026-07-27T15:39:39Z",
+   "avg_ns": 79088419701,
+   "stddev_ns": 90694156,
+   "avg_ts": 6.473771,
+   "stddev_ts": 0.007424,
+   "samples_ns": [
+    79024289865,
+    79152549538
+   ],
+   "samples_ts": [
+    6.47902,
+    6.46852
+   ]
+  },
+  {
+   "build_commit": "e07b3ec",
+   "build_number": 2,
+   "cpu_info": "unknown",
+   "gpu_info": "",
+   "backends": "CPU",
+   "model_filename": "/vol/gguf/neutrino-8b-cons3b25-fv5.gguf",
+   "model_type": "qwen3 8B FV5 - 3.25 bpw Fermion five-value ternary",
+   "model_size": 4087058432,
+   "model_n_params": 8190735360,
+   "n_batch": 2048,
+   "n_ubatch": 512,
+   "n_threads": 16,
+   "cpu_mask": "0x0",
+   "cpu_strict": false,
+   "poll": 50,
+   "type_k": "f16",
+   "type_v": "f16",
+   "n_gpu_layers": -1,
+   "n_cpu_moe": 0,
+   "split_mode": "layer",
+   "main_gpu": 0,
+   "no_kv_offload": false,
+   "flash_attn": -1,
+   "devices": "auto",
+   "tensor_split": "0.00",
+   "tensor_buft_overrides": "none",
+   "load_mode": "mmap",
+   "embeddings": false,
+   "no_op_offload": 0,
+   "no_host": false,
+   "fit_target": 0,
+   "fit_min_ctx": 0,
+   "n_prompt": 0,
+   "n_gen": 128,
+   "n_depth": 0,
+   "test_time": "2026-07-27T15:43:36Z",
+   "avg_ns": 25262016201,
+   "stddev_ns": 350847779,
+   "avg_ts": 5.067384,
+   "stddev_ts": 0.070378,
+   "samples_ns": [
+    25510103045,
+    25013929357
+   ],
+   "samples_ts": [
+    5.01762,
+    5.11715
+   ]
+  }
+ ],
+ "smoke_rc": 0,
+ "smoke_text": "Paris. The capital of France is Paris. The capital of France is Paris. The capital of France is Paris. The capital of France is Paris. The capital of France is Paris. The capital of France is Paris. The capital of France",
+ "threads": 16,
+ "cpu": "unknown",
+ "nproc": 32,
+ "wall_s": 304.1,
+ "ts": "2026-07-27T15:44:42Z"
+}

gguf/receipts/convert_8b.json

@@ -0,0 +1,44 @@
+{
+ "status": "CONVERT_PASS",
+ "container": {
+  "name": "neutrino-8b_v4.bin",
+  "sha256": "016c6f362ad237a8cf4043601efbc1e766574f76ea58691e78fdef51b4155fa0"
+ },
+ "f32_gguf": {
+  "name": "neutrino-8b-cons3b25-f32.gguf",
+  "bytes": 32768897920
+ },
+ "out": {
+  "name": "neutrino-8b-cons3b25-fv5.gguf",
+  "bytes": 4093015136,
+  "sha256": "1c13a34360b2531d28821fb6aee41708f99a040215a2522af37213c6c8c87211"
+ },
+ "tensors": {
+  "fv5": 252,
+  "fv5b": 2,
+  "f32": 145,
+  "total": 399,
+  "bitwise_checked": 399
+ },
+ "tied_output_omitted": false,
+ "quantized_params": 8190427136,
+ "effective_bpw_quantized": 3.9979,
+ "header": {
+  "magic": 1129599572,
+  "version": 4,
+  "arch": 3,
+  "n_layers": 36,
+  "hidden": 4096,
+  "n_heads": 32,
+  "n_kv_heads": 8,
+  "head_dim": 128,
+  "rotary_dims": 128,
+  "intermediate": 12288,
+  "vocab": 151936,
+  "max_pos": 40960,
+  "rms_norm_eps": 9.999999974752427e-07,
+  "rope_theta": 1000000.0,
+  "eok": 2
+ },
+ "wall_seconds": 174.6
+}

gguf/receipts/gate_8b_fv5.json

@@ -0,0 +1,105 @@
+{
+  "model": "/vol/gguf/neutrino-8b-cons3b25-fv5.gguf",
+  "steps": 128,
+  "n_threads": 16,
+  "load_seconds": 0.46,
+  "kv_type": "f32",
+  "prompts": [
+    {
+      "prompt_ids": [1,791,1283,315,220,17,42,99],
+      "free_ids": [198,1,791,1283,315,220,17,42,198,1,791,1283,315,220,17,42,198,1,791,1283,315,220,17,42,198,1,791,1283,315,220,17,42,198,1,791,1283,315,220,17,42,198,1,791,1283,315,220,17,42,198,1,791,1283,315,220,17,42,198,1,791,1283,315,220,17,42,198,1,791,1283,315,220,17,42,198,1,791,1283,315,220,17,42,198,1,791,1283,315,220,17,42,198,1,791,1283,315,220,17,42,198,1,791,1283,315,220,17,42,198,1,791,1283,315,220,17,42,198,1,791,1283,315,220,17,42,198,1,791,1283,315,220,17,42],
+      "free_min_top2_margin": 0.128316,
+      "prompt_seconds": 1.369,
+      "gen_seconds": 24.789,
+      "free_match": true,
+      "first_divergence": -1,
+      "forced_mismatch_count": 0,
+      "forced_mismatches": []
+    },
+    {
+      "prompt_ids": [1,9707,374,264,1296,13,28,7],
+      "free_ids": [16,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15],
+      "free_min_top2_margin": 0.083496,
+      "prompt_seconds": 1.316,
+      "gen_seconds": 28.711,
+      "free_match": true,
+      "first_divergence": -1,
+      "forced_mismatch_count": 0,
+      "forced_mismatches": []
+    },
+    {
+      "prompt_ids": [1,2610,525,498,1091,11,16,3],
+      "free_ids": [323,498,525,537,11,17,3,323,498,525,537,11,18,3,323,498,525,537,11,19,3,323,498,525,537,11,20,3,323,498,525,537,11,21,3,323,498,525,537,11,22,3,323,498,525,537,11,23,3,323,498,525,537,11,24,3,323,498,525,537,11,16,15,3,323,498,525,537,11,16,16,3,323,498,525,537,11,16,17,3,323,498,525,537,11,16,18,3,323,498,525,537,11,16,19,3,323,498,525,537,11,16,20,3,323,498,525,537,11,16,21,3,323,498,525,537,11,16,22,3,323,498,525,537,11,16,23,3],
+      "free_min_top2_margin": 0.070037,
+      "prompt_seconds": 1.516,
+      "gen_seconds": 31.581,
+      "free_match": true,
+      "first_divergence": -1,
+      "forced_mismatch_count": 0,
+      "forced_mismatches": []
+    },
+    {
+      "prompt_ids": [785,6722,315,9625,374],
+      "free_ids": [12095,13,576,6722,315,9625,374,12095,13,576,6722,315,9625,374,12095,13,576,6722,315,9625,374,12095,13,576,6722,315,9625,374,12095,13,576,6722,315,9625,374,12095,13,576,6722,315,9625,374,12095,13,576,6722,315,9625,374,12095,13,576,6722,315,9625,374,12095,13,576,6722,315,9625,374,12095,13,576,6722,315,9625,374,12095,13,576,6722,315,9625,374,12095,13,576,6722,315,9625,374,12095,13,576,6722,315,9625,374,12095,13,576,6722,315,9625,374,12095,13,576,6722,315,9625,374,12095,13,576,6722,315,9625,374,12095,13,576,6722,315,9625,374,12095,13,576,6722,315,9625,374,12095,13],
+      "free_min_top2_margin": 0.439365,
+      "prompt_seconds": 0.952,
+      "gen_seconds": 31.652,
+      "free_match": true,
+      "first_divergence": -1,
+      "forced_mismatch_count": 0,
+      "forced_mismatches": []
+    },
+    {
+      "prompt_ids": [641,264,28727,33161,11,264,2613,21730,11105],
+      "free_ids": [264,11580,448,264,4911,3343,13,576,11580,594,7329,374,9761,448,264,5827,315,31340,11,1817,9334,3432,264,3108,3084,315,220,16,4982,13,576,21730,13166,429,279,11580,702,264,2790,315,220,16,15,15,15,31340,13,4354,11,279,21730,1083,13686,429,1045,31340,525,537,9434,504,279,21730,594,2309,13,44763,11,279,31340,429,525,537,9434,525,1846,429,525,537,23942,311,894,1008,9334,13,758,1008,4244,11,264,9334,374,537,9434,421,432,374,537,8433,311,894,1008,9334,553,264,3108,13,2585,1657,31340,525,9434,504,279,21730,594,2309,1939,1249,11625,419,3491,11,582,1184,311,8253,1246,1657],
+      "free_min_top2_margin": 0.053864,
+      "prompt_seconds": 1.460,
+      "gen_seconds": 25.266,
+      "free_match": true,
+      "first_divergence": -1,
+      "forced_mismatch_count": 0,
+      "forced_mismatches": []
+    },
+    {
+      "prompt_ids": [750,75698,1445,1648],
+      "free_ids": [198,262,421,308,621,220,15,510,286,470,220,15,198,262,421,308,621,220,16,510,286,470,220,16,198,262,770,510,286,470,75698,1445,12,16,8,488,75698,1445,12,17,692,77,284,526,5384,445,6269,279,1372,315,3793,25,40964,75326,39345,1445,340,13874,19324,1986,2038,18653,264,729,1565,75326,39345,1445,46186,429,47417,279,55129,79683,1372,1667,50262,13,576,729,374,1221,2598,448,279,1196,594,1946,369,279,1372,315,3793,13,576,2038,374,1632,1737,36684,323,5646,1465,11589,369,8318,11127,13,576,729,374,11050,323,4278,369,678,6785,25780,13,576,2038,374,1083,4135,311,1349,323,3535],
+      "free_min_top2_margin": 0.067368,
+      "prompt_seconds": 0.689,
+      "gen_seconds": 25.640,
+      "free_match": true,
+      "first_divergence": -1,
+      "forced_mismatch_count": 0,
+      "forced_mismatches": []
+    },
+    {
+      "prompt_ids": [785,2326,6872,315,29845,78911,1584,429],
+      "free_ids": [4802,374,1585,2771,11,429,279,5106,315,8628,8317,374,504,1550,9315,311,3347,9315,11,323,429,279,2086,2329,315,29845,78911,374,429,47502,12703,13,220,576,1156,2329,315,29845,78911,374,279,2329,315,28611,315,4802,13,220,576,2086,2329,315,29845,78911,374,279,2329,315,7703,47502,13,220,576,4843,2329,315,29845,78911,374,429,279,47502,315,264,1849,646,2581,18472,11,1172,5263,11,323,429,279,47502,315,264,1849,304,28387,55311,374,518,1181,7192,13,220,576,1156,2329,315,29845,78911,374,279,2329,315,28611,315,4802,13,220,576,2086,2329,315,29845,78911,374,279,2329,315,7703,47502,13,220,576],
+      "free_min_top2_margin": 0.021589,
+      "prompt_seconds": 1.308,
+      "gen_seconds": 25.809,
+      "free_match": true,
+      "first_divergence": -1,
+      "forced_mismatch_count": 0,
+      "forced_mismatches": []
+    },
+    {
+      "prompt_ids": [12522,5193,264,882,11,304,264,11340,14126,553,279,9396,11],
+      "free_ids": [1052,12163,264,3908,3743,6941,444,10524,13,2932,572,3881,369,1059,40228,323,2948,369,279,17951,13,7209,6556,11,1340,1035,15156,705,1573,38393,11,11435,311,279,11321,311,8844,311,279,16876,323,2666,279,9278,1948,1059,44613,13,6252,6930,7702,572,264,2613,272,994,1380,279,3015,572,19300,323,279,511,988,6436,15186,832,304,279,39020,13,1084,572,1052,429,1340,1035,1477,279,1429,6233,58849,11,1075,13673,511,988,6436,11,9472,315,33638,6660,11,323,1496,264,2421,1560,3435,429,1035,1136,98243,3123,979,1340,2684,2238,3265,382,3966,1899,11,1393,23966,279,272,994,11,444,10524,13686,264,43697,2770,396],
+      "free_min_top2_margin": 0.015932,
+      "prompt_seconds": 2.088,
+      "gen_seconds": 25.561,
+      "free_match": true,
+      "first_divergence": -1,
+      "forced_mismatch_count": 0,
+      "forced_mismatches": []
+    }
+  ],
+  "totals": {
+    "prompt_tokens": 63,
+    "gen_tokens": 1024,
+    "prompt_tok_per_s": 5.89,
+    "gen_tok_per_s": 4.68,
+    "forced_mismatch_total": 0,
+    "all_free_match": true
+  }
+}

gguf/receipts/gateverdict_8b_fv5.json

@@ -0,0 +1,17 @@
+{
+ "model": "8b",
+ "variant": "fv5",
+ "verdict": "PASS",
+ "all_free_match": true,
+ "forced_mismatch_total": 0,
+ "gen_tok_per_s": 4.68,
+ "prompt_tok_per_s": 5.89,
+ "flips": [],
+ "unexplained": 0,
+ "gguf_sha256": "1c13a34360b2531d28821fb6aee41708f99a040215a2522af37213c6c8c87211",
+ "ref_trajectory_sha256": "96041dbdd766f1536303f5a8bd7577bd60ea8412008f525f2e8f9d3499980638",
+ "threads": 16,
+ "cpu": "unknown",
+ "wall_s": 463.4,
+ "ts": "2026-07-27T15:39:37Z"
+}

gguf/receipts/gguf_spec_quickstart_k16.json

@@ -0,0 +1,141 @@
+{
+ "receipt": "llama.cpp NATIVE speculative decoding (its own sampling-based acceptance, NOT our bit-gated certification) with fermion-fv5 fork + banked fv5 GGUFs: 8B-wbase target, 0.6B-base draft",
+ "fork_head": "e07b3ec135c1f90c64584e0ea2dc983e47094ab9",
+ "draft_flag_used": [
+  "--spec-draft-n-max",
+  "16"
+ ],
+ "target": "/gguf_ro/gguf/neutrino-8b-wbase-fv5.gguf",
+ "draft": "/gguf_ro/gguf/neutrino-0.6b-base-fv5.gguf",
+ "threads": 16,
+ "cpu": "unknown",
+ "nproc": 32,
+ "results": {
+  "facts": {
+   "prompt": "The three laws of thermodynamics state that",
+   "n_tok": 128,
+   "baseline": {
+    "prompt_ms": 997.53,
+    "prompt_n": 8,
+    "prompt_tok_s": 8.02,
+    "eval_ms": 19152.78,
+    "eval_n": 127,
+    "eval_tok_s": 6.63,
+    "rc": 0
+   },
+   "baseline_text_head": "energy is conserved, that the entropy of an isolated system can never decrease, and that the entropy of an isolated system can never increase. The first law is ",
+   "spec": {
+    "prompt_ms": 58409.31,
+    "prompt_n": 484,
+    "prompt_tok_s": 8.29,
+    "encoded_ms_tok_s": {
+     "tokens": 8,
+     "seconds": 1.082,
+     "tok_s": 7.392
+    },
+    "decoded_ms_tok_s": {
+     "tokens": 134,
+     "seconds": 68.869,
+     "tok_s": 1.946
+    },
+    "n_draft": 16,
+    "n_predict": 134,
+    "n_drafted": 448,
+    "n_accept": 105,
+    "accept_pct": 23.438,
+    "rc": 0,
+    "draft_flag": [
+     "--spec-draft-n-max",
+     "16"
+    ]
+   },
+   "spec_tail": "The three laws of thermodynamics state that energy is conserved, that the entropy of an isolated system can never decrease, and that the entropy of an isolated system can never increase. The first law is the conservation of energy, which states that energy cannot be created or destroyed, only transformed. The second law states that the entropy of an isolated system can never decrease. The third law states that the entropy of an isolated system can never increase. The second law is also known as the law of increasing entropy. The third law is also known as the law of zero entropy. The second law is also known as the law of increasing entropy. The third law is also known as the law of zero entropy. The second\n\n\n\n\n0.00.623.260 W load: control-looking token: 128247 '</s>' was not control-type; this is probably a bug in the model. its type will be overridden\n0.02.775.851 W load: control-looking token: 128247 '</s>' was not control-type; this is probably a bug in the model. its type will be overridden\n1.13.679.397 I encoded    8 tokens in    1.082 seconds, speed:    7.392 t/s\n1.13.679.399 I decoded  134 tokens in   68.869 seconds, speed:    1.946 t/s\n1.13.679.399 I \n1.13.679.400 I n_draft   = 16\n1.13.679.400 I n_predict = 134\n1.13.679.408 I n_drafted = 448\n1.13.679.408 I n_accept  = 105\n1.13.679.409 I accept    = 23.438%\n1.13.679.409 I \n1.13.679.409 I draft:\n\n1.13.679.424 I \n1.13.679.424 I target:\n\n1.13.679.431 I common_perf_print:    sampling time =      29.13 ms\n1.13.679.431 I common_perf_print:    samplers time =       7.43 ms /   134 tokens\n1.13.679.433 I common_perf_print:        load time =    1559.85 ms\n1.13.679.434 I common_perf_print: prompt eval time =   58409.31 ms /   484 tokens (  120.68 ms per token,     8.29 tokens per second)\n1.13.679.435 I common_perf_print:        eval time =       0.00 ms /     1 runs   (    0.00 ms per token,      inf tokens per second)\n1.13.679.435 I common_perf_print:       total time =   71586.90 ms /   485 tokens\n1.13.679.436 I common_perf_print: unaccounted time =   13148.46 ms /  18.4 %      (total - sampling - prompt eval - eval) / (total)\n1.13.679.436 I common_perf_print:    graphs reused =         27",
+   "speedup": 0.294
+  },
+  "prose": {
+   "prompt": "Once upon a time, in a quiet village by the sea,",
+   "n_tok": 128,
+   "baseline": {
+    "prompt_ms": 1553.17,
+    "prompt_n": 13,
+    "prompt_tok_s": 8.37,
+    "eval_ms": 19023.4,
+    "eval_n": 127,
+    "eval_tok_s": 6.68,
+    "rc": 0
+   },
+   "baseline_text_head": "there lived a young girl named Lila. She was known for her kindness and curiosity. One day, while exploring the forest near her home, she stumbled upon a hidden",
+   "spec": {
+    "prompt_ms": 123089.45,
+    "prompt_n": 999,
+    "prompt_tok_s": 8.12,
+    "encoded_ms_tok_s": {
+     "tokens": 13,
+     "seconds": 1.699,
+     "tok_s": 7.653
+    },
+    "decoded_ms_tok_s": {
+     "tokens": 131,
+     "seconds": 143.874,
+     "tok_s": 0.911
+    },
+    "n_draft": 16,
+    "n_predict": 131,
+    "n_drafted": 928,
+    "n_accept": 72,
+    "accept_pct": 7.759,
+    "rc": 0,
+    "draft_flag": [
+     "--spec-draft-n-max",
+     "16"
+    ]
+   },
+   "spec_tail": "Once upon a time, in a quiet village by the sea, there lived a young girl named Lila. She was known for her kindness and curiosity. One day, while exploring the forest near her home, she stumbled upon a hidden cave. Inside, she found a glowing orb that seemed to pulse with a soft light. Intrigued, she picked it up and noticed that it was not just a regular rock. It was a crystal that emitted a faint light. As she held it closer, she noticed that the light was not just a natural glow but something more. It was as if the crystal was alive, responding to her touch. \n\nLila was fascinated and decided to take the crystal home. She placed\n\n\n\n\n0.00.585.445 W load: control-looking token: 128247 '</s>' was not control-type; this is probably a bug in the model. its type will be overridden\n0.02.549.802 W load: control-looking token: 128247 '</s>' was not control-type; this is probably a bug in the model. its type will be overridden\n2.29.032.790 I encoded   13 tokens in    1.699 seconds, speed:    7.653 t/s\n2.29.032.794 I decoded  131 tokens in  143.874 seconds, speed:    0.911 t/s\n2.29.032.794 I \n2.29.032.802 I n_draft   = 16\n2.29.032.802 I n_predict = 131\n2.29.032.803 I n_drafted = 928\n2.29.032.803 I n_accept  = 72\n2.29.032.804 I accept    = 7.759%\n2.29.032.804 I \n2.29.032.804 I draft:\n\n2.29.032.822 I \n2.29.032.822 I target:\n\n2.29.032.829 I common_perf_print:    sampling time =      32.72 ms\n2.29.032.830 I common_perf_print:    samplers time =       7.62 ms /   131 tokens\n2.29.032.832 I common_perf_print:        load time =    1519.90 ms\n2.29.032.833 I common_perf_print: prompt eval time =  123089.45 ms /   999 tokens (  123.21 ms per token,     8.12 tokens per second)\n2.29.032.834 I common_perf_print:        eval time =       0.00 ms /     1 runs   (    0.00 ms per token,      inf tokens per second)\n2.29.032.834 I common_perf_print:       total time =  147009.52 ms /  1000 tokens\n2.29.032.837 I common_perf_print: unaccounted time =   23887.34 ms /  16.2 %      (total - sampling - prompt eval - eval) / (total)\n2.29.032.838 I common_perf_print:    graphs reused =         57",
+   "speedup": 0.136
+  },
+  "code": {
+   "prompt": "def fibonacci(n):",
+   "n_tok": 128,
+   "baseline": {
+    "prompt_ms": 511.22,
+    "prompt_n": 4,
+    "prompt_tok_s": 7.82,
+    "eval_ms": 19258.57,
+    "eval_n": 127,
+    "eval_tok_s": 6.59,
+    "rc": 0
+   },
+   "baseline_text_head": "if n < 0:\n        return 0\n    if n == 0:\n        return 0\n    if n == 1:\n        return 1\n    return fibonacci(n-1) + fibonacci(n-2)\n\ndef fibonacci(n):\n    # b",
+   "spec": {
+    "prompt_ms": 74903.85,
+    "prompt_n": 616,
+    "prompt_tok_s": 8.22,
+    "encoded_ms_tok_s": {
+     "tokens": 4,
+     "seconds": 0.598,
+     "tok_s": 6.693
+    },
+    "decoded_ms_tok_s": {
+     "tokens": 132,
+     "seconds": 88.867,
+     "tok_s": 1.485
+    },
+    "n_draft": 16,
+    "n_predict": 132,
+    "n_drafted": 576,
+    "n_accept": 95,
+    "accept_pct": 16.493,
+    "rc": 0,
+    "draft_flag": [
+     "--spec-draft-n-max",
+     "16"
+    ]
+   },
+   "spec_tail": "    # base case\n    if n == 0:\n        return 0\n    if n == 1:\n        return 1\n    # recursive case\n    return fibonacci(n-1) + fibonacci(n-2)\n\n# test cases\nprint(fibonacci(0))  # 0\nprint(fibonacci(1))  # 1\nprint(fib\n\n\n\n\n0.00.572.699 W load: control-looking token: 128247 '</s>' was not control-type; this is probably a bug in the model. its type will be overridden\n0.02.535.311 W load: control-looking token: 128247 '</s>' was not control-type; this is probably a bug in the model. its type will be overridden\n1.32.870.731 I encoded    4 tokens in    0.598 seconds, speed:    6.693 t/s\n1.32.870.732 I decoded  132 tokens in   88.867 seconds, speed:    1.485 t/s\n1.32.870.733 I \n1.32.870.733 I n_draft   = 16\n1.32.870.733 I n_predict = 132\n1.32.870.734 I n_drafted = 576\n1.32.870.734 I n_accept  = 95\n1.32.870.734 I accept    = 16.493%\n1.32.870.734 I \n1.32.870.734 I draft:\n\n1.32.870.747 I \n1.32.870.754 I target:\n\n1.32.870.798 I common_perf_print:    sampling time =      30.78 ms\n1.32.870.801 I common_perf_print:    samplers time =       6.95 ms /   132 tokens\n1.32.870.807 I common_perf_print:        load time =    1545.72 ms\n1.32.870.809 I common_perf_print: prompt eval time =   74903.85 ms /   616 tokens (  121.60 ms per token,     8.22 tokens per second)\n1.32.870.810 I common_perf_print:        eval time =       0.00 ms /     1 runs   (    0.00 ms per token,      inf tokens per second)\n1.32.870.811 I common_perf_print:       total time =   90831.76 ms /   617 tokens\n1.32.870.811 I common_perf_print: unaccounted time =   15897.13 ms /  17.5 %      (total - sampling - prompt eval - eval) / (total)\n1.32.870.812 I common_perf_print:    graphs reused =         35",
+   "speedup": 0.225
+  }
+ },
+ "wall_s": 449.6,
+ "ts": "2026-07-25T16:44:01Z",
+ "_annotation_20260726": "HONESTY NOTE (successor session): this quickstart was measured against the RETIRED W-baseline cut (neutrino-8b-wbase-fv5.gguf). The published pack is the s50 product cut (210195d7...). llama.cpp-native speculation was an honest NULL either way (0.14-0.66x); numbers kept for reference only, not re-run (README already labels the section EXPERIMENTAL)."
+}

gguf/receipts/gguf_spec_quickstart_k4.json

@@ -0,0 +1,141 @@
+{
+ "receipt": "llama.cpp NATIVE speculative decoding (its own sampling-based acceptance, NOT our bit-gated certification) with fermion-fv5 fork + banked fv5 GGUFs: 8B-wbase target, 0.6B-base draft",
+ "fork_head": "e07b3ec135c1f90c64584e0ea2dc983e47094ab9",
+ "draft_flag_used": [
+  "--spec-draft-n-max",
+  "4"
+ ],
+ "target": "/gguf_ro/gguf/neutrino-8b-wbase-fv5.gguf",
+ "draft": "/gguf_ro/gguf/neutrino-0.6b-base-fv5.gguf",
+ "threads": 16,
+ "cpu": "unknown",
+ "nproc": 32,
+ "results": {
+  "facts": {
+   "prompt": "The three laws of thermodynamics state that",
+   "n_tok": 128,
+   "baseline": {
+    "prompt_ms": 1245.64,
+    "prompt_n": 8,
+    "prompt_tok_s": 6.42,
+    "eval_ms": 23778.72,
+    "eval_n": 127,
+    "eval_tok_s": 5.34,
+    "rc": 0
+   },
+   "baseline_text_head": "energy is conserved, that the entropy of an isolated system can never decrease, and that the entropy of an isolated system can never increase. The first law is ",
+   "spec": {
+    "prompt_ms": 32972.91,
+    "prompt_n": 208,
+    "prompt_tok_s": 6.31,
+    "encoded_ms_tok_s": {
+     "tokens": 8,
+     "seconds": 1.358,
+     "tok_s": 5.892
+    },
+    "decoded_ms_tok_s": {
+     "tokens": 132,
+     "seconds": 37.378,
+     "tok_s": 3.531
+    },
+    "n_draft": 4,
+    "n_predict": 132,
+    "n_drafted": 160,
+    "n_accept": 91,
+    "accept_pct": 56.875,
+    "rc": 0,
+    "draft_flag": [
+     "--spec-draft-n-max",
+     "4"
+    ]
+   },
+   "spec_tail": "The three laws of thermodynamics state that energy is conserved, that the entropy of an isolated system can never decrease, and that the entropy of an isolated system can never increase. The first law is the conservation of energy, which states that energy cannot be created or destroyed, only transformed. The second law states that the entropy of an isolated system can never decrease. The third law states that the entropy of an isolated system can never increase. The second law is also known as the law of increasing entropy. The third law is also known as the law of zero entropy. The second law is also known as the law of increasing entropy. The third law is also known as the law of zero entropy.\n\n\n\n\n0.00.771.178 W load: control-looking token: 128247 '</s>' was not control-type; this is probably a bug in the model. its type will be overridden\n0.03.414.343 W load: control-looking token: 128247 '</s>' was not control-type; this is probably a bug in the model. its type will be overridden\n0.43.601.940 I encoded    8 tokens in    1.358 seconds, speed:    5.892 t/s\n0.43.601.942 I decoded  132 tokens in   37.378 seconds, speed:    3.531 t/s\n0.43.601.942 I \n0.43.601.943 I n_draft   = 4\n0.43.601.943 I n_predict = 132\n0.43.601.943 I n_drafted = 160\n0.43.601.943 I n_accept  = 91\n0.43.601.954 I accept    = 56.875%\n0.43.601.954 I \n0.43.601.954 I draft:\n\n0.43.601.972 I \n0.43.601.972 I target:\n\n0.43.601.979 I common_perf_print:    sampling time =      53.66 ms\n0.43.601.980 I common_perf_print:    samplers time =      10.54 ms /   132 tokens\n0.43.601.983 I common_perf_print:        load time =    2121.14 ms\n0.43.601.984 I common_perf_print: prompt eval time =   32972.91 ms /   208 tokens (  158.52 ms per token,     6.31 tokens per second)\n0.43.601.985 I common_perf_print:        eval time =       0.00 ms /     1 runs   (    0.00 ms per token,      inf tokens per second)\n0.43.601.985 I common_perf_print:       total time =   40811.34 ms /   209 tokens\n0.43.601.986 I common_perf_print: unaccounted time =    7784.78 ms /  19.1 %      (total - sampling - prompt eval - eval) / (total)\n0.43.601.987 I common_perf_print:    graphs reused =         39",
+   "speedup": 0.661
+  },
+  "prose": {
+   "prompt": "Once upon a time, in a quiet village by the sea,",
+   "n_tok": 128,
+   "baseline": {
+    "prompt_ms": 1974.15,
+    "prompt_n": 13,
+    "prompt_tok_s": 6.59,
+    "eval_ms": 23545.97,
+    "eval_n": 127,
+    "eval_tok_s": 5.39,
+    "rc": 0
+   },
+   "baseline_text_head": "there lived a young girl named Lila. She was known for her kindness and curiosity. One day, while exploring the forest near her home, she stumbled upon a hidden",
+   "spec": {
+    "prompt_ms": 49207.44,
+    "prompt_n": 308,
+    "prompt_tok_s": 6.26,
+    "encoded_ms_tok_s": {
+     "tokens": 13,
+     "seconds": 2.134,
+     "tok_s": 6.093
+    },
+    "decoded_ms_tok_s": {
+     "tokens": 131,
+     "seconds": 55.128,
+     "tok_s": 2.376
+    },
+    "n_draft": 4,
+    "n_predict": 131,
+    "n_drafted": 236,
+    "n_accept": 71,
+    "accept_pct": 30.085,
+    "rc": 0,
+    "draft_flag": [
+     "--spec-draft-n-max",
+     "4"
+    ]
+   },
+   "spec_tail": "Once upon a time, in a quiet village by the sea, there lived a young girl named Lila. She was known for her kindness and curiosity. One day, while exploring the forest near her home, she stumbled upon a hidden cave. Inside, she found a glowing orb that seemed to pulse with a soft light. Intrigued, she picked it up and noticed that it was not just a regular rock. It was a crystal that emitted a faint light. As she held it closer, she noticed that the light was not just a natural glow but something more. It was as if the crystal was alive, responding to her touch. \n\nLila was fascinated and decided to take the crystal home. She placed\n\n\n\n\n0.00.762.994 W load: control-looking token: 128247 '</s>' was not control-type; this is probably a bug in the model. its type will be overridden\n0.03.368.212 W load: control-looking token: 128247 '</s>' was not control-type; this is probably a bug in the model. its type will be overridden\n1.01.817.657 I encoded   13 tokens in    2.134 seconds, speed:    6.093 t/s\n1.01.817.697 I decoded  131 tokens in   55.128 seconds, speed:    2.376 t/s\n1.01.817.697 I \n1.01.817.698 I n_draft   = 4\n1.01.817.698 I n_predict = 131\n1.01.817.698 I n_drafted = 236\n1.01.817.698 I n_accept  = 71\n1.01.817.699 I accept    = 30.085%\n1.01.817.699 I \n1.01.817.699 I draft:\n\n1.01.817.715 I \n1.01.817.715 I target:\n\n1.01.817.723 I common_perf_print:    sampling time =      54.68 ms\n1.01.817.723 I common_perf_print:    samplers time =      10.39 ms /   131 tokens\n1.01.817.725 I common_perf_print:        load time =    2083.05 ms\n1.01.817.726 I common_perf_print: prompt eval time =   49207.44 ms /   308 tokens (  159.76 ms per token,     6.26 tokens per second)\n1.01.817.727 I common_perf_print:        eval time =       0.00 ms /     1 runs   (    0.00 ms per token,      inf tokens per second)\n1.01.817.728 I common_perf_print:       total time =   59095.53 ms /   309 tokens\n1.01.817.729 I common_perf_print: unaccounted time =    9833.40 ms /  16.6 %      (total - sampling - prompt eval - eval) / (total)\n1.01.817.729 I common_perf_print:    graphs reused =         58",
+   "speedup": 0.441
+  },
+  "code": {
+   "prompt": "def fibonacci(n):",
+   "n_tok": 128,
+   "baseline": {
+    "prompt_ms": 639.29,
+    "prompt_n": 4,
+    "prompt_tok_s": 6.26,
+    "eval_ms": 23422.95,
+    "eval_n": 127,
+    "eval_tok_s": 5.42,
+    "rc": 0
+   },
+   "baseline_text_head": "if n < 0:\n        return 0\n    if n == 0:\n        return 0\n    if n == 1:\n        return 1\n    return fibonacci(n-1) + fibonacci(n-2)\n\ndef fibonacci(n):\n    # b",
+   "spec": {
+    "prompt_ms": 36454.87,
+    "prompt_n": 229,
+    "prompt_tok_s": 6.28,
+    "encoded_ms_tok_s": {
+     "tokens": 4,
+     "seconds": 0.728,
+     "tok_s": 5.494
+    },
+    "decoded_ms_tok_s": {
+     "tokens": 130,
+     "seconds": 42.11,
+     "tok_s": 3.087
+    },
+    "n_draft": 4,
+    "n_predict": 130,
+    "n_drafted": 180,
+    "n_accept": 84,
+    "accept_pct": 46.667,
+    "rc": 0,
+    "draft_flag": [
+     "--spec-draft-n-max",
+     "4"
+    ]
+   },
+   "spec_tail": "    # base case\n    if n == 0:\n        return 0\n    if n == 1:\n        return 1\n    # recursive case\n    return fibonacci(n-1) + fibonacci(n-2)\n\n# test cases\nprint(fibonacci(0))  # 0\nprint(fibonacci(1))  # 1\nprint\n\n\n\n\n0.00.784.120 W load: control-looking token: 128247 '</s>' was not control-type; this is probably a bug in the model. its type will be overridden\n0.03.369.496 W load: control-looking token: 128247 '</s>' was not control-type; this is probably a bug in the model. its type will be overridden\n0.47.355.247 I encoded    4 tokens in    0.728 seconds, speed:    5.494 t/s\n0.47.355.249 I decoded  130 tokens in   42.110 seconds, speed:    3.087 t/s\n0.47.355.249 I \n0.47.355.250 I n_draft   = 4\n0.47.355.250 I n_predict = 130\n0.47.355.250 I n_drafted = 180\n0.47.355.250 I n_accept  = 84\n0.47.355.251 I accept    = 46.667%\n0.47.355.251 I \n0.47.355.251 I draft:\n\n0.47.355.269 I \n0.47.355.269 I target:\n\n0.47.355.276 I common_perf_print:    sampling time =      51.98 ms\n0.47.355.277 I common_perf_print:    samplers time =      10.86 ms /   130 tokens\n0.47.355.279 I common_perf_print:        load time =    2064.72 ms\n0.47.355.280 I common_perf_print: prompt eval time =   36454.87 ms /   229 tokens (  159.19 ms per token,     6.28 tokens per second)\n0.47.355.281 I common_perf_print:        eval time =       0.00 ms /     1 runs   (    0.00 ms per token,      inf tokens per second)\n0.47.355.282 I common_perf_print:       total time =   44627.08 ms /   230 tokens\n0.47.355.283 I common_perf_print: unaccounted time =    8120.24 ms /  18.2 %      (total - sampling - prompt eval - eval) / (total)\n0.47.355.283 I common_perf_print:    graphs reused =         44",
+   "speedup": 0.57
+  }
+ },
+ "wall_s": 324.4,
+ "ts": "2026-07-25T16:50:05Z",
+ "_annotation_20260726": "HONESTY NOTE (successor session): this quickstart was measured against the RETIRED W-baseline cut (neutrino-8b-wbase-fv5.gguf). The published pack is the s50 product cut (210195d7...). llama.cpp-native speculation was an honest NULL either way (0.14-0.66x); numbers kept for reference only, not re-run (README already labels the section EXPERIMENTAL)."
+}

gguf/receipts/ref_8b.json

@@ -0,0 +1,26 @@
+{
+ "model": "8b",
+ "dtype": "float32",
+ "steps": 128,
+ "trajectory_sha256": "96041dbdd766f1536303f5a8bd7577bd60ea8412008f525f2e8f9d3499980638",
+ "continuity_vs_banked_fp16": [
+  {
+   "prompt": 0,
+   "fp16_match": false,
+   "first_divergence": 0
+  },
+  {
+   "prompt": 1,
+   "fp16_match": false,
+   "first_divergence": 1
+  },
+  {
+   "prompt": 2,
+   "fp16_match": false,
+   "first_divergence": 1
+  }
+ ],
+ "wall_s": 1701.4,
+ "cpu": "unknown",
+ "ts": "2026-07-27T15:26:19Z"
+}

gguf/receipts_ifcs50_retired/bench_8b.json

@@ -0,0 +1,112 @@
+{
+ "model": "8b",
+ "bench": [
+  {
+   "build_commit": "e07b3ec",
+   "build_number": 2,
+   "cpu_info": "unknown",
+   "gpu_info": "",
+   "backends": "CPU",
+   "model_filename": "/vol/gguf/neutrino-8b-ifc50-fv5.gguf",
+   "model_type": "qwen3 8B FV5 - 3.25 bpw Fermion five-value ternary",
+   "model_size": 4087058432,
+   "model_n_params": 8190735360,
+   "n_batch": 2048,
+   "n_ubatch": 512,
+   "n_threads": 16,
+   "cpu_mask": "0x0",
+   "cpu_strict": false,
+   "poll": 50,
+   "type_k": "f16",
+   "type_v": "f16",
+   "n_gpu_layers": -1,
+   "n_cpu_moe": 0,
+   "split_mode": "layer",
+   "main_gpu": 0,
+   "no_kv_offload": false,
+   "flash_attn": -1,
+   "devices": "auto",
+   "tensor_split": "0.00",
+   "tensor_buft_overrides": "none",
+   "load_mode": "mmap",
+   "embeddings": false,
+   "no_op_offload": 0,
+   "no_host": false,
+   "fit_target": 0,
+   "fit_min_ctx": 0,
+   "n_prompt": 512,
+   "n_gen": 0,
+   "n_depth": 0,
+   "test_time": "2026-07-26T18:21:45Z",
+   "avg_ns": 79011453606,
+   "stddev_ns": 10228708,
+   "avg_ts": 6.480073,
+   "stddev_ts": 0.000839,
+   "samples_ns": [
+    79004220817,
+    79018686395
+   ],
+   "samples_ts": [
+    6.48067,
+    6.47948
+   ]
+  },
+  {
+   "build_commit": "e07b3ec",
+   "build_number": 2,
+   "cpu_info": "unknown",
+   "gpu_info": "",
+   "backends": "CPU",
+   "model_filename": "/vol/gguf/neutrino-8b-ifc50-fv5.gguf",
+   "model_type": "qwen3 8B FV5 - 3.25 bpw Fermion five-value ternary",
+   "model_size": 4087058432,
+   "model_n_params": 8190735360,
+   "n_batch": 2048,
+   "n_ubatch": 512,
+   "n_threads": 16,
+   "cpu_mask": "0x0",
+   "cpu_strict": false,
+   "poll": 50,
+   "type_k": "f16",
+   "type_v": "f16",
+   "n_gpu_layers": -1,
+   "n_cpu_moe": 0,
+   "split_mode": "layer",
+   "main_gpu": 0,
+   "no_kv_offload": false,
+   "flash_attn": -1,
+   "devices": "auto",
+   "tensor_split": "0.00",
+   "tensor_buft_overrides": "none",
+   "load_mode": "mmap",
+   "embeddings": false,
+   "no_op_offload": 0,
+   "no_host": false,
+   "fit_target": 0,
+   "fit_min_ctx": 0,
+   "n_prompt": 0,
+   "n_gen": 128,
+   "n_depth": 0,
+   "test_time": "2026-07-26T18:25:42Z",
+   "avg_ns": 25045562535,
+   "stddev_ns": 103809881,
+   "avg_ts": 5.11073,
+   "stddev_ts": 0.021183,
+   "samples_ns": [
+    25118967206,
+    24972157864
+   ],
+   "samples_ts": [
+    5.09575,
+    5.12571
+   ]
+  }
+ ],
+ "smoke_rc": 0,
+ "smoke_text": "Paris. The capital of France is Paris. The capital of France is Paris. The capital of France is Paris. The capital of France is Paris. The capital of France is Paris. The capital of France is Paris. The capital of France",
+ "threads": 16,
+ "cpu": "unknown",
+ "nproc": 32,
+ "wall_s": 301.3,
+ "ts": "2026-07-26T18:26:46Z"
+}

gguf/receipts_ifcs50_retired/convert_8b.json

@@ -0,0 +1,44 @@
+{
+ "status": "CONVERT_PASS",
+ "container": {
+  "name": "neutrino-8b_v4.bin",
+  "sha256": "39787a2e15dcffa20135c7c1bb1b8ed55c8632263f8457f3395f55d52007a3be"
+ },
+ "f32_gguf": {
+  "name": "neutrino-8b-ifc50-f32.gguf",
+  "bytes": 32768897920
+ },
+ "out": {
+  "name": "neutrino-8b-ifc50-fv5.gguf",
+  "bytes": 4093015136,
+  "sha256": "7dda995047dc70540d2d83f2c464dd118fff62eef1aab36ae71ceb3cc972e5d0"
+ },
+ "tensors": {
+  "fv5": 252,
+  "fv5b": 2,
+  "f32": 145,
+  "total": 399,
+  "bitwise_checked": 399
+ },
+ "tied_output_omitted": false,
+ "quantized_params": 8190427136,
+ "effective_bpw_quantized": 3.9979,
+ "header": {
+  "magic": 1129599572,
+  "version": 4,
+  "arch": 3,
+  "n_layers": 36,
+  "hidden": 4096,
+  "n_heads": 32,
+  "n_kv_heads": 8,
+  "head_dim": 128,
+  "rotary_dims": 128,
+  "intermediate": 12288,
+  "vocab": 151936,
+  "max_pos": 40960,
+  "rms_norm_eps": 9.999999974752427e-07,
+  "rope_theta": 1000000.0,
+  "eok": 2
+ },
+ "wall_seconds": 177.3
+}

gguf/receipts_ifcs50_retired/gateverdict_8b_fv5.json

@@ -0,0 +1,17 @@
+{
+ "model": "8b",
+ "variant": "fv5",
+ "verdict": "PASS",
+ "all_free_match": true,
+ "forced_mismatch_total": 0,
+ "gen_tok_per_s": 5.16,
+ "prompt_tok_per_s": 6.08,
+ "flips": [],
+ "unexplained": 0,
+ "gguf_sha256": "7dda995047dc70540d2d83f2c464dd118fff62eef1aab36ae71ceb3cc972e5d0",
+ "ref_trajectory_sha256": "3568b5a38cc72ec8b4cb9b61eba729b60a538647fad3ae455151b7c7a0620597",
+ "threads": 16,
+ "cpu": "unknown",
+ "wall_s": 422.5,
+ "ts": "2026-07-26T18:21:43Z"
+}

gguf/receipts_ifcs50_retired/ref_8b.json

@@ -0,0 +1,26 @@
+{
+ "model": "8b",
+ "dtype": "float32",
+ "steps": 128,
+ "trajectory_sha256": "3568b5a38cc72ec8b4cb9b61eba729b60a538647fad3ae455151b7c7a0620597",
+ "continuity_vs_banked_fp16": [
+  {
+   "prompt": 0,
+   "fp16_match": false,
+   "first_divergence": 0
+  },
+  {
+   "prompt": 1,
+   "fp16_match": false,
+   "first_divergence": 0
+  },
+  {
+   "prompt": 2,
+   "fp16_match": false,
+   "first_divergence": 0
+  }
+ ],
+ "wall_s": 1756.0,
+ "cpu": "unknown",
+ "ts": "2026-07-26T18:08:52Z"
+}

mlx/MANIFEST.json

@@ -0,0 +1,143 @@
+{
+ "note": "MLX pack provenance: file -> bytes/sha256/source. Weights entry is declarative (not duplicated in this subfolder).",
+ "generated_utc": "2026-07-25T16:52:04Z",
+ "weights_container": {
+  "file": "neutrino-8b_v4.bin",
+  "status": "GATED ON THE RELEASE CONTAINER (cons3-B25 product bake, FOUNDER-AUTHORISED PROMOTE 2026-07-27): pathgate + refgate both PASS 2026-07-27 (fused-vs-mxops 32-token greedy IDENTICAL; TF rel max 0.000%, argmax 9/9, greedy 24/24, 0 flips) \u2014 receipts pathgate_8b_cons3b25.json / refgate_8b_cons3b25.json.",
+  "gated_on_file": "neutrino-8b_v4.bin",
+  "gated_on_bytes": 3875404812,
+  "gated_on_sha256": "016c6f362ad237a8cf4043601efbc1e766574f76ea58691e78fdef51b4155fa0",
+  "gated_on_source": "internal lab archive: archive/consolidation_3/export_v4_B25/neutrino-8b_v4.bin",
+  "retired_gates": [
+   {
+    "note": "RETIRED 2026-07-27 \u2014 d25 product bake; the pack was NEVER re-pinned to ifc-s50 even though its gates ran (receipts pathgate_8b_ifc50.json / refgate_8b_ifc50.json stayed in the lane dir and were never copied into the pack). Both are superseded by cons3-B25.",
+    "gated_on_sha256": "06af07b5f17c832186c95fce6252691ec84dbbc9320a4d4ce9ce989547c06e9b"
+   },
+   {
+    "note": "RETIRED 2026-07-27 \u2014 ifc-s50 ship brain, gated 2026-07-26 but never published in this manifest; superseded by the cons3-B25 promote.",
+    "gated_on_sha256": "39787a2e15dcffa20135c7c1bb1b8ed55c8632263f8457f3395f55d52007a3be"
+   },
+   {
+    "note": "RETIRED 2026-07-26 ~10:45Z \u2014 s50 gate, superseded by d25 (round-2 winner).",
+    "gated_on_sha256": "fe85f93214376354f118a83235eeff6bc5d40e112474afacbd3e0310768b08d5"
+   },
+   {
+    "note": "RETIRED 2026-07-26 \u2014 original correctness gate ran on the W-baseline container (identical bytes count, different brain).",
+    "gated_on_file": "wbase_v4.bin",
+    "gated_on_sha256": "5af0c75b14fbac020324768455ce660a92110f4f71f507635fd160dd0b03f0a1",
+    "gated_on_source": "internal lab archive: archive/labarchive/dspec8b/artifacts/wbase_v4.bin"
+   }
+  ]
+ },
+ "kernel_provenance": {
+  "vendored": "fermion_mlx/trit_kernels.py",
+  "repo_file": "kernels/metal/trit_kernels.py",
+  "sha256": "c56db6dd5e3743d19c54411f5f0b2dfef135f7805906a62cc4e40f1ee5e80f27",
+  "relation": "byte-identical"
+ },
+ "files": {
+  "README.md": {
+   "bytes": 5949,
+   "sha256": "1ab11a6f6e1a915db38da647ecbc66b524fed9e474b80067c60daf3d89dfaafe",
+   "source": "pack file"
+  },
+  "fermion_mlx/__init__.py": {
+   "bytes": 2306,
+   "sha256": "55d5e0a1efd92802c28f03ab526a01d4c26493fa5e523c495d2076ff56e4985a",
+   "source": "NEW: load()/generate()/chat() API"
+  },
+  "fermion_mlx/__main__.py": {
+   "bytes": 7347,
+   "sha256": "87190c0c23c712bfe5b31bc54d2dadd69a971c5d8ff8e66f05ba1fd2dbc1352f",
+   "source": "NEW: CLI (gen/chat/gate/cachegate/pathgate/bench) + spec/specgate/specbench modes (spec_paths)"
+  },
+  "fermion_mlx/arch3.py": {
+   "bytes": 7541,
+   "sha256": "a831e8a24b2b9a986b393d1c316aac66a3399a082a57176254b2feeae032f8cd",
+   "source": "NEW (mlx_packs lane 2026-07-25): fused per-head QK-RMSNorm+rope+KV-append kernel + s8 v3 x-staged int8 unembed"
+  },
+  "fermion_mlx/container.py": {
+   "bytes": 6059,
+   "sha256": "c5b352184ba9ddf9a3e424731226cb7dcb9901d3a1516c67d4557953b0101f2f",
+   "source": "NEW: TRTC v4 arch-3 reader (layout per scripts/expand_trtc_v4_to_hf.py + kernels/gpu_e2e/runtime8b.py)"
+  },
+  "fermion_mlx/gates.py": {
+   "bytes": 7454,
+   "sha256": "faf8634b0bd3afec5c4422decdbd8cc04fbb7f3426f70cdd6626fd6b177aa8b4",
+   "source": "NEW: house V1 refgate / cachegate / pathgate"
+  },
+  "fermion_mlx/mbatch.py": {
+   "bytes": 6492,
+   "sha256": "c9ec8d37f1cdc0554cda01cefbc435e67525779c79e0dac7fd760e7919e6fdd2",
+   "source": "NEW (spec_paths 2026-07-25): M-token batched trit/s8 GEMMs for speculative verify (one weight read per k+1 positions)"
+  },
+  "fermion_mlx/model.py": {
+   "bytes": 12748,
+   "sha256": "9488f8194ce8be006ce05dfaf6118353de44005ce54f38f73a0908ccac2749da",
+   "source": "NEW: MetalTritQwen3 walker (fused primary path + mx.fast-ops reference twin)"
+  },
+  "fermion_mlx/spec.py": {
+   "bytes": 11207,
+   "sha256": "969e946d5d2eeb63d44afa4c62dd2453d87fa14e83b936bc673482b59ee3b745",
+   "source": "NEW (spec_paths 2026-07-25): EXPERIMENTAL greedy-exact speculative decoding (0.6B drafts, 8B verifies), exactness-gated"
+  },
+  "fermion_mlx/trit_kernels.py": {
+   "bytes": 36881,
+   "sha256": "c56db6dd5e3743d19c54411f5f0b2dfef135f7805906a62cc4e40f1ee5e80f27",
+   "source": "VENDORED byte-identical from kernels/metal/trit_kernels.py (repo sha c56db6dd5e3743d19c54411f5f0b2dfef135f7805906a62cc4e40f1ee5e80f27) \u2014 the banked five-value Metal GEMV stack"
+  },
+  "merges.txt": {
+   "bytes": 1671853,
+   "sha256": "8831e4f1a044471340f7c0a83d7bd71306a5b867e95fd870f74d0c5308a904d5",
+   "source": "donor Qwen/Qwen3-8B (same files as the parent tree root)"
+  },
+  "receipts/bench_8b_wbase_m5_16gb_memcapped.json": {
+   "bytes": 599,
+   "sha256": "9d3b153ec49dce92846fb9140fc38267ed04a08b5adcda91f2036ce94869b555",
+   "source": "gate/bench receipt (mlx_packs lane, 2026-07-25)"
+  },
+  "receipts/pathgate_8b_wbase.json": {
+   "bytes": 612,
+   "sha256": "50d6584a9ba2dae87bf502f2e637916a604be72db473fc89977fb8e1aaf3413b",
+   "source": "gate/bench receipt (mlx_packs lane, 2026-07-25)"
+  },
+  "receipts/refgate_8b_wbase.json": {
+   "bytes": 1909,
+   "sha256": "851da3bb5c093182eb56532711dd9a95123ca44260e53de951b27c8b96eaf7a4",
+   "source": "gate/bench receipt (mlx_packs lane, 2026-07-25)"
+  },
+  "receipts/specbench_8b_0p6b_m5.json": {
+   "bytes": 826,
+   "sha256": "c36ef09659d8c7690d53c23d065943103a95417890f8defbd01e629d7b5feeca",
+   "source": "spec gate/bench receipt (spec_paths lane, 2026-07-25)"
+  },
+  "receipts/specgate_8b_0p6b.json": {
+   "bytes": 705,
+   "sha256": "64bcb90fe965835bc78887d873d3cfd0677b76c6d72cda04a84e295efee7c10c",
+   "source": "spec gate/bench receipt (spec_paths lane, 2026-07-25)"
+  },
+  "requirements.txt": {
+   "bytes": 191,
+   "sha256": "1cf4d1fa581aaa5deae0568f88388c51166bbd69e7a89080b5a53488a7ef39b6",
+   "source": "pack file"
+  },
+  "tokenizer.json": {
+   "bytes": 11422654,
+   "sha256": "aeb13307a71acd8fe81861d94ad54ab689df773318809eed3cbe794b4492dae4",
+   "source": "donor Qwen/Qwen3-8B (same files as the parent tree root)"
+  },
+  "tokenizer_config.json": {
+   "bytes": 9732,
+   "sha256": "d5d09f07b48c3086c508b30d1c9114bd1189145b74e982a265350c923acd8101",
+   "source": "donor Qwen/Qwen3-8B (same files as the parent tree root)"
+  },
+  "vocab.json": {
+   "bytes": 2776833,
+   "sha256": "ca10d7e9fb3ed18575dd1e277a2579c16d108e32f27439684afa0e10b1440910",
+   "source": "donor Qwen/Qwen3-8B (same files as the parent tree root)"
+  }
+ },
+ "addenda": [
+  "2026-07-25 spec_paths: EXPERIMENTAL --spec speculative decoding added (new modules mbatch.py/spec.py + CLI modes + README section). Exactness-gated: specgate 6/6 token-identical vs plain (receipts). Existing gate battery re-verified on the updated package."
+ ]
+}

mlx/README.md

@@ -0,0 +1,133 @@
+# Neutrino-8B — MLX pack (Apple silicon)
+
+Run the [Neutrino-8B](../README.md) five-value (sub-2-bit) container
+natively from Python on Apple silicon: MLX + our custom Metal kernels. The
+~3.61 GiB TRTC v4 arch-3 container is memory-mapped and the five-value
+{0, ±s_lo, ±s_hi} planes stay bit-packed at rest — decode happens inside
+the GEMV kernels; nothing in the decode path is fp16/fp32 weight material.
+
+> [!IMPORTANT]
+> **PRODUCT-CONTAINER RE-GATE COMPLETE (2026-07-27).** The final shipping
+> container is the cons3-B25 ship brain (`neutrino-8b_v4.bin`,
+> 3,875,404,812 bytes, sha256 `016c6f36…55fa0`, baked 2026-07-27 from
+> consolidation-3 arm B step 25 — see the parent card). This MLX pack's
+> runtime + kernels are **correctness-gated on that exact container**:
+> both gates were re-run against it on an Apple M5 (16 GB, MLX 0.31.2,
+> 6 GiB cap) and both PASS — receipts `receipts/pathgate_8b_cons3b25.json`
+> and `receipts/refgate_8b_cons3b25.json`. The runtime is geometry-driven
+> (header-dispatched), so the swap involved no code change.
+>
+> RETIRED, do **not** verify against: ifc-s50 `39787a2e…07a3be`, d25
+> `06af07b5…c06e9b`, s50 `fe85f932…768b08d5`, wbase `5af0c75b…03f0a1`.
+
+## Install & run
+
+```bash
+pip install -r requirements.txt        # mlx, numpy, transformers
+python -m fermion_mlx --model neutrino-8b_v4.bin --mode chat \
+    --tokenizer . --prompt "Why is the sky blue?"
+```
+
+Python API:
+
+```python
+import fermion_mlx
+from transformers import AutoTokenizer
+
+model = fermion_mlx.load("neutrino-8b_v4.bin")   # ~4.2 GiB unified memory
+tok = AutoTokenizer.from_pretrained(".")
+text, stats = fermion_mlx.chat(model, tok,
+                               [{"role": "user", "content": "hi"}])
+```
+
+Memory: the loaded model holds ~3.8 GiB of packed planes + int8 embedding
+lanes (untied: separate embed_in and lm_head records) plus the KV cache
+(`maxseq` × 302 KiB/layer fp32). A 16 GB Mac runs it; 8 GB does not.
+`--mem-limit-gb` makes the process fail fast instead of pressuring the
+machine.
+
+## What runs on the GPU
+
+Identical stack to the Neutrino-0.6B MLX pack (one geometry-generic
+runtime): five-value 3-bit-planar GEMV kernels (v7 LUT decode) with fused
+RMSNorm/SwiGLU/residual epilogues, the fused arch-3 per-head
+Q/K-RMSNorm + rope + KV-append kernel, int8 embed/unembed lanes with
+threadgroup x-staging, MLX SDPA with block-grown windows, `mx.compile`d
+step.
+
+## Correctness receipts
+
+House rule: greedy streams token-identical to the container's own fp32
+expansion reference; near-tie flips at tiny logit margins are the only
+tolerated class, each documented with its margin. Receipts in `receipts/`
+(gated on the **shipping** container `016c6f36…55fa0`, re-run 2026-07-27):
+
+| gate | reference | result |
+|---|---|---|
+| V1 refgate | fp32 HF expansion of **this** container (eager attn), teacher-forced 9 pos + 24-token greedy | **PASS — TF rel err 0.000% (max), cos 1.000000, argmax 9/9, greedy 24/24, 0 flips** |
+| pathgate | fused-kernel path vs pure `mx.fast`-ops twin | 32-token greedy IDENTICAL |
+
+## Speed (honest numbers, with venue)
+
+- Apple-silicon M-series decode receipt for the 8B: **25.0 tok/s median**
+  (128-token greedy × 3 runs, 24.3–25.6, peak MLX memory **3.67 GiB**),
+  measured under a strict 6 GiB memory cap on a 16 GB M5 MacBook, macOS,
+  MLX 0.31.2, 2026-07-25 (wbase container;
+  `receipts/bench_8b_wbase_m5_16gb_memcapped.json`). Decode is
+  memory-bandwidth-bound, so this is representative for M5-class machines;
+  a fuller M-series story (longer runs, larger windows, bigger-RAM
+  machines) lands with the Metal arch-3 port rollout. The CUDA receipts in
+  the parent tree (H100: 379 tok/s plain greedy, up to 650+ tok/s with
+  certified speculative decoding — **research-harness numbers**, measured
+  on the research stack, not the shipped binaries) and the shipped CPU
+  `bin/` fermion-run path remain the primary 8B performance story.
+
+## EXPERIMENTAL: speculative decoding with the 0.6B pack as draft
+
+The package ships a `--spec` mode where the Neutrino-0.6B pack drafts and
+this 8B verifies, with the house **greedy-exact acceptance rule**: a draft
+token is accepted iff it equals the verifier's argmax at that position, so
+the emitted stream is exactness-gated against plain decoding (receipt:
+`receipts/specgate_8b_0p6b.json` — 3 prompts × {32, 256} tokens, spec vs
+plain **token-identical 6/6**, both models in one process under a 6 GiB
+MLX cap).
+
+```bash
+python -m fermion_mlx --model neutrino-8b_v4.bin \
+    --draft-model neutrino-0.6b_v4.bin --mode spec \
+    --tokenizer . --prompt "..." --mem-limit-gb 6     # --spec-k 4 default
+```
+
+Honest numbers (M5 MacBook 16 GB, 6 GiB cap, k=4, 512-token greedy × 3
+runs, medians; `receipts/specbench_8b_0p6b_m5.json`):
+
+| text type | plain 8B | 8B + 0.6B draft | speedup | acceptance |
+|---|---|---|---|---|
+| facts | 22.0 tok/s | **25.7 tok/s** | **1.17×** | 74% |
+| chat-ish | 17.5 tok/s | 14.7 tok/s | 0.84× | 44% |
+| prose | 17.9 tok/s | 12.2 tok/s | 0.68× | 30% |
+
+Read before enabling: the speedup is real only on text where the 0.6B
+drafts well (repetitive/factual continuations). Acceptance is
+text-dependent because the draft is the *base* 0.6B, not a model distilled
+from the 8B; and the current batched-verify kernel costs ~2.8× a single
+step (M-wide mask-convert decode is compute-bound), so break-even needs
+~2.9 accepted tokens/round. A LUT-based batched decode + adaptive k are
+the known day-2 upgrades. This flag never changes outputs (exactness rule
+above) — worst case it changes speed. Not memory contention: both-model
+peak stayed under 4.3 GiB of the 6 GiB cap.
+
+## Files
+
+- `fermion_mlx/` — loader/runtime package (same bytes as the 0.6B pack's).
+- tokenizer files — donor Qwen3-8B (shipped in the parent tree root too).
+- `receipts/` — gate receipts (JSON), kernel-source sha sidecar.
+- `MANIFEST.json` — file-by-file provenance + shas.
+
+Weights: not duplicated in this subfolder — the parent `MANIFEST.json`
+governs the container (interim vs final product swap included).
+
+## License
+
+Apache-2.0 (this pack's code). Weights per the parent card (Apache-2.0,
+derivative of Qwen/Qwen3-8B). `bin/` EULA unchanged.

mlx/fermion_mlx/__init__.py

@@ -0,0 +1,129 @@
+"""fermion_mlx — run Fermion Research TRTC v4 arch-3 (Qwen3-family) ternary
+containers on Apple silicon via MLX + custom Metal kernels.
+
+    import fermion_mlx
+    model = fermion_mlx.load("neutrino-0p6b_v4_base.bin")
+    text = fermion_mlx.generate(model, tokenizer, "The capital of France is",
+                                max_tokens=64)
+
+The five-value {0, ±s_lo, ±s_hi} weights stay bit-packed at rest and are
+decoded inside the GEMV kernels; nothing is expanded to fp16/fp32 weights.
+Kernel version: env TRIT_METAL_V (default 7 = the banked LUT-decode bodies).
+"""
+import os
+
+# choose the crown kernel bodies before the kernel module is imported
+os.environ.setdefault("TRIT_METAL_V", "7")
+
+from .model import MetalTritQwen3  # noqa: E402
+
+
+def load(container_path, maxseq=1024, verbose=True):
+    """Memory-map a TRTC v4 arch-3 container and build the Metal model."""
+    return MetalTritQwen3(container_path, maxseq=maxseq, verbose=verbose)
+
+
+DEFAULT_EOS = (151645, 151643)  # <|im_end|>, <|endoftext|>
+
+
+def _as_ids(x):
+    """Normalise whatever a tokenizer handed back into a flat list of ids.
+
+    transformers >= 4.56 flipped `apply_chat_template(tokenize=True)` to
+    return a BatchEncoding instead of a list of ids (return_dict defaults to
+    True). requirements.txt says `transformers>=4.53`, so a fresh install gets
+    the new behaviour and the old code fed a BatchEncoding straight into
+    `model.prefill`, which died with
+    `int() argument must be ... not 'tokenizers.Encoding'`.
+    """
+    if hasattr(x, "input_ids"):
+        x = x.input_ids
+    elif isinstance(x, dict) and "input_ids" in x:
+        x = x["input_ids"]
+    if len(x) and isinstance(x[0], (list, tuple)):   # batched -> first row
+        x = x[0]
+    return [int(t) for t in x]
+
+
+def _rp_greedy(model, ids, n, rp, eos=None):
+    """Greedy decode with the CTRL/HF multiplicative repetition penalty.
+
+    Byte-for-byte the rule the graded MLX battery used
+    (handoffs/results_0p6b_chatv2/scripts/local_mlx_battery_v2.py:30-54,
+    `rp_greedy`): the penalty applies to every id SEEN SO FAR in the whole
+    context, not to a 256-token window — that is the MLX-side convention and
+    it is what the banked MLX numbers on the model card were produced at.
+
+    This path materialises the logits every step, so it forfeits the fused
+    fast path's one-step async lookahead. It is only taken when rp != 1.0;
+    `model.generate` (rp = 1.0) is untouched, so the banked tok/s receipts
+    still describe the default.
+    """
+    import time
+
+    import mlx.core as mx
+    import numpy as np
+
+    eos = set(eos or ())
+    mask = model.new_mask()
+    x, pos0 = model.prefill(ids, mask)
+    seen = set(int(t) for t in ids)
+    toks = []
+    t0 = time.perf_counter()
+    for i in range(n):
+        pb = mx.array([pos0 + i], dtype=mx.int32)
+        W = model._window(pos0 + i)
+        nt, xn, lg = model.step_compiled(x, pb, mask, W)
+        lgn = np.array(lg, copy=True)
+        idxs = np.fromiter(seen, dtype=np.int64)
+        vals = lgn[idxs]
+        lgn[idxs] = np.where(vals > 0, vals / rp, vals * rp)
+        tsel = int(lgn.argmax())
+        toks.append(tsel)
+        if tsel in eos:
+            break
+        x = model.embed(tsel)
+        seen.add(tsel)
+    return toks, time.perf_counter() - t0
+
+
+def _decode(model, tokenizer, ids, max_tokens, eos, rep_penalty):
+    if rep_penalty and float(rep_penalty) != 1.0:
+        toks, dt = _rp_greedy(model, ids, max_tokens, float(rep_penalty),
+                              eos=eos)
+    else:
+        toks, dt = model.generate(ids, max_tokens, eos=eos)
+    if eos:
+        cut = next((i for i, t in enumerate(toks) if t in eos), len(toks))
+        toks = toks[:cut]
+    text = tokenizer.decode(toks)
+    rate = (len(toks) or 1) / dt if dt > 0 else 0.0
+    return text, {"tokens": len(toks), "seconds": dt, "tok_s": rate}
+
+
+def generate(model, tokenizer, prompt, max_tokens=256, stop_on_eos=True,
+             rep_penalty=1.0):
+    """Greedy completion of a plain-text prompt. Returns (text, stats).
+
+    `rep_penalty` > 1.0 enables the CTRL-style repetition penalty the graded
+    MLX battery ran at (1.05 on the chat SKU); 1.0, the default, is the
+    untouched pure-argmax fast path.
+    """
+    ids = _as_ids(tokenizer(prompt))
+    eos = set(DEFAULT_EOS) if stop_on_eos else None
+    return _decode(model, tokenizer, ids, max_tokens, eos, rep_penalty)
+
+
+def chat(model, tokenizer, messages, max_tokens=256, rep_penalty=1.0):
+    """Chat completion via the donor chat template (thinking off).
+
+    `rep_penalty` as in `generate`; the chat SKU's card documents 1.05.
+    """
+    try:
+        raw = tokenizer.apply_chat_template(messages, add_generation_prompt=True,
+                                            enable_thinking=False)
+    except TypeError:
+        raw = tokenizer.apply_chat_template(messages, add_generation_prompt=True)
+    ids = _as_ids(raw)
+    return _decode(model, tokenizer, ids, max_tokens, set(DEFAULT_EOS),
+                   rep_penalty)

mlx/fermion_mlx/__main__.py

@@ -0,0 +1,177 @@
+#!/usr/bin/env python3
+"""fermion_mlx CLI.
+
+  python -m fermion_mlx --model x.bin --mode gen   --prompt "..."
+  python -m fermion_mlx --model x.bin --mode chat  --prompt "..." --tokenizer DIR
+  python -m fermion_mlx --model x.bin --mode chat  --prompt "..." --tokenizer DIR \
+      --rep-penalty 1.05      # the graded chat-SKU config
+  python -m fermion_mlx --model x.bin --mode gate      --ref wbase_ref.npz
+  python -m fermion_mlx --model x.bin --mode cachegate --cache hf_greedy_cache.json
+  python -m fermion_mlx --model x.bin --mode pathgate
+  python -m fermion_mlx --model x.bin --mode bench --runs 5 --gen-tokens 512
+
+EXPERIMENTAL speculative decoding (0.6B drafts, exactness-gated):
+  python -m fermion_mlx --model 8b.bin --draft-model 0.6b.bin --mode spec \
+      --prompt "..." --tokenizer DIR --mem-limit-gb 6
+  python -m fermion_mlx --model 8b.bin --draft-model 0.6b.bin --mode specgate \
+      --tokenizer DIR --mem-limit-gb 6 --receipt specgate.json
+  python -m fermion_mlx --model 8b.bin --draft-model 0.6b.bin --mode specbench \
+      --tokenizer DIR --mem-limit-gb 6 --receipt specbench.json
+
+Gate receipts are written next to --receipt (JSON) when given.
+"""
+import argparse
+import json
+import sys
+import time
+
+import mlx.core as mx
+
+import fermion_mlx
+from fermion_mlx.gates import refgate, cachegate, pathgate
+
+HOUSE_PROMPT = "The key idea behind ternary neural networks is"
+# tokenizer-free fallback: Qwen3-tokenized HOUSE_PROMPT (donor-verified ids)
+HOUSE_IDS = [785, 1376, 4522, 4815, 71617, 658, 29728, 14155, 374]
+
+
+def _tok(args):
+    from transformers import AutoTokenizer
+    return AutoTokenizer.from_pretrained(args.tokenizer)
+
+
+def main():
+    ap = argparse.ArgumentParser()
+    ap.add_argument("--model", required=True)
+    ap.add_argument("--mode", default="gen",
+                    choices=["gen", "chat", "gate", "cachegate", "pathgate",
+                             "bench", "spec", "specgate", "specbench"])
+    ap.add_argument("--draft-model", default="",
+                    help="draft container for --mode spec* (e.g. the 0.6B pack)")
+    ap.add_argument("--spec-k", type=int, default=4,
+                    help="draft tokens per speculative round")
+    ap.add_argument("--prompt", default=HOUSE_PROMPT)
+    ap.add_argument("--tokenizer", default="Qwen/Qwen3-0.6B")
+    ap.add_argument("--ref", default="")
+    ap.add_argument("--cache", default="")
+    ap.add_argument("--receipt", default="")
+    ap.add_argument("--tie-tol", type=float, default=0.04, dest="tie_tol")
+    ap.add_argument("--max-flips", type=int, default=8, dest="max_flips")
+    ap.add_argument("--gen-tokens", type=int, default=512)
+    ap.add_argument("--runs", type=int, default=5)
+    ap.add_argument("--maxseq", type=int, default=1024)
+    ap.add_argument("--no-tokenizer", action="store_true",
+                    help="use the pinned house prompt ids (no transformers)")
+    ap.add_argument("--mem-limit-gb", type=float, default=0.0,
+                    help="hard MLX memory limit; the process fails fast "
+                         "instead of pressuring the machine (house OOM rule)")
+    ap.add_argument("--rep-penalty", type=float, default=1.0,
+                    dest="rep_penalty",
+                    help="CTRL-style repetition penalty over the whole "
+                         "context, the rule the graded MLX battery ran at "
+                         "(1.05 on the chat SKU). 1.0 (default) = the "
+                         "untouched pure-argmax fast path.")
+    args = ap.parse_args()
+
+    if args.mem_limit_gb > 0:
+        mx.set_memory_limit(int(args.mem_limit_gb * 2**30))
+        print(f"[mem] MLX memory limit set to {args.mem_limit_gb:.1f} GiB")
+
+    model = fermion_mlx.load(args.model, maxseq=args.maxseq)
+
+    def save(rec):
+        if args.receipt:
+            json.dump(rec, open(args.receipt, "w"), indent=1)
+            print(f"receipt -> {args.receipt}")
+
+    if args.mode in ("spec", "specgate", "specbench"):
+        from fermion_mlx.spec import SpecDecoder, specgate, specbench
+        assert args.draft_model, "--mode spec* needs --draft-model"
+        draft = fermion_mlx.load(args.draft_model, maxseq=args.maxseq)
+        tok = _tok(args)
+        if args.mode == "specgate":
+            rec = specgate(model, draft, tok, k=args.spec_k,
+                           receipt=args.receipt or None)
+            print(f"[specgate] {rec['verdict']}")
+            sys.exit(0 if rec["verdict"] == "PASS" else 1)
+        if args.mode == "specbench":
+            rec = specbench(model, draft, tok, k=args.spec_k,
+                            n=args.gen_tokens, runs=args.runs,
+                            receipt=args.receipt or None)
+            for t, v in rec["types"].items():
+                print(f"[specbench {t}] plain {v['plain_median_tok_s']} -> "
+                      f"spec {v['spec_median_tok_s']} tok/s "
+                      f"({v['speedup']}x, acc {v['acceptance_median']})")
+            return
+        sd = SpecDecoder(model, draft, k=args.spec_k)
+        ids = tok(args.prompt, add_special_tokens=False).input_ids
+        toks, dt, st = sd.generate(ids, args.gen_tokens)
+        print(tok.decode(toks))
+        print(f"[spec: {len(toks)} tok in {dt*1e3:.0f} ms -> "
+              f"{len(toks)/dt:.1f} tok/s | acceptance {st['acceptance']:.3f} "
+              f"| {st['tokens_per_round']} tok/round]")
+        return
+
+    if args.mode == "gate":
+        ok, rec = refgate(model, args.ref, args.tie_tol, args.max_flips)
+        rec["mode"], rec["model"] = "refgate", args.model
+        save(rec)
+        sys.exit(0 if ok else 1)
+
+    if args.mode == "cachegate":
+        ok, rec = cachegate(model, args.model, args.cache, args.tie_tol,
+                            args.max_flips)
+        rec["mode"], rec["model"] = "cachegate", args.model
+        save(rec)
+        sys.exit(0 if ok else 1)
+
+    if args.mode == "pathgate":
+        ids = (HOUSE_IDS if args.no_tokenizer else
+               fermion_mlx._as_ids(_tok(args)(args.prompt)))
+        ok, rec = pathgate(model, ids, n=32)
+        rec["mode"], rec["model"] = "pathgate", args.model
+        save(rec)
+        sys.exit(0 if ok else 1)
+
+    if args.mode == "bench":
+        ids = (HOUSE_IDS if args.no_tokenizer else
+               fermion_mlx._as_ids(_tok(args)(args.prompt)))
+        n = args.gen_tokens
+        model.generate(ids, 16)                     # warmup + kernel JIT
+        rates, runs = [], []
+        for r in range(args.runs):
+            toks, dt = model.generate(ids, n)       # no EOS stop: full budget
+            rates.append(n / dt)
+            runs.append({"run": r, "tokens": n, "seconds": dt, "tok_s": n / dt})
+            print(f"  run {r}: {n} tok in {dt*1e3:.0f} ms -> {rates[-1]:.1f} tok/s")
+        rates.sort()
+        med = rates[len(rates) // 2]
+        peak = mx.get_peak_memory() / 2**30
+        print(f"[bench] median {med:.1f} tok/s over {args.runs} runs "
+              f"({n}-token greedy), peak mem {peak:.2f} GiB")
+        save({"mode": "bench", "model": args.model, "prompt_ids": ids,
+              "gen_tokens": n, "runs": runs, "median_tok_s": med,
+              "peak_mem_gib": peak,
+              "utc": time.strftime("%Y-%m-%dT%H:%M:%SZ", time.gmtime())})
+        return
+
+    tok = _tok(args)
+    if args.mode == "gen":
+        text, st = fermion_mlx.generate(model, tok, args.prompt,
+                                        max_tokens=args.gen_tokens,
+                                        rep_penalty=args.rep_penalty)
+        print(text)
+        print(f"[{st['tokens']} tokens in {st['seconds']*1e3:.0f} ms -> "
+              f"{st['tok_s']:.1f} tok/s]")
+    else:
+        text, st = fermion_mlx.chat(model, tok,
+                                    [{"role": "user", "content": args.prompt}],
+                                    max_tokens=args.gen_tokens,
+                                    rep_penalty=args.rep_penalty)
+        print(text)
+        print(f"[{st['tokens']} tokens in {st['seconds']*1e3:.0f} ms -> "
+              f"{st['tok_s']:.1f} tok/s]")
+
+
+if __name__ == "__main__":
+    main()

mlx/fermion_mlx/arch3.py

@@ -0,0 +1,183 @@
+#!/usr/bin/env python3
+"""Arch-3 (Qwen3) Metal kernel: fused per-head Q/K-RMSNorm + NeoX rope +
+KV-cache append, one dispatch per decode step.
+
+The Qwen3 arch delta vs arch-1 is the per-head RMSNorm applied to the qkv
+GEMV output BEFORE rope (HF order: q_norm/k_norm over head_dim, weights
+shared across heads). This kernel is the arch-3 twin of
+trit_kernels.rope_append: one simdgroup per head; q/k heads compute the
+head's rms via simd_sum then rope the normed values; v heads copy raw
+values into the cache. kc/vc/mask are written in place at position pos
+(stream-serial ordering with the consumer SDPA — the banked rope_append
+pattern; correctness enforced by the e2e gates).
+"""
+import mlx.core as mx
+
+_CACHE = {}
+SG_PER_TG = 8
+
+
+def _s8_source_v3(rows, cols, rs, sg_per_tg, fuse_norm, eps, rpsg=8):
+    """arch-3 lane addition: int8 GEMV with threadgroup x staging.
+
+    The vendored s8 v2 kernel re-reads the full x vector from device memory
+    once per simdgroup (rows/rpsg simdgroups x cols floats — for the 151936-
+    row Qwen3 unembed that is +50% of the weight bytes). v3 stages the
+    effective x (rmsnorm applied) into threadgroup memory once per
+    THREADGROUP, tile by tile; every simdgroup then streams only its int8
+    rows. Requires rows % (rpsg * sg_per_tg) == 0 (true for vocab 151936)."""
+    assert rs % 4 == 0 and cols % 4 == 0 and rows % (rpsg * sg_per_tg) == 0
+    tile = min(cols, 1024)
+    assert cols % tile == 0
+    ntiles = cols // tile
+    nthreads = sg_per_tg * 32
+    if fuse_norm:
+        norm_pre = f"""
+    threadgroup float ssq_sh[{sg_per_tg}];
+    {{
+        float ssq = 0.0f;
+        for (uint c = tid; c < {cols}u; c += {nthreads}u) {{
+            float v = x[c]; ssq = metal::fma(v, v, ssq);
+        }}
+        ssq = metal::simd_sum(ssq);
+        if (lane == 0u) ssq_sh[sg] = ssq;
+        threadgroup_barrier(metal::mem_flags::mem_threadgroup);
+        float tt = 0.0f;
+        for (uint i = 0u; i < {sg_per_tg}u; ++i) tt += ssq_sh[i];
+        rms = metal::rsqrt(tt / {float(cols)}f + {eps:.9g}f);
+    }}
+"""
+        stage = f"xb[cl] = x[c] * nw[c] * rms;"
+    else:
+        norm_pre = ""
+        stage = "xb[cl] = x[c];"
+    return f"""
+    uint tid  = thread_position_in_threadgroup.x;
+    uint lane = tid & 31u;
+    uint sg   = tid >> 5u;
+    uint row0 = (threadgroup_position_in_grid.x * {sg_per_tg}u + sg) * {rpsg}u;
+    float rms = 1.0f;
+{norm_pre}
+    threadgroup float xb[{tile}];
+    float acc[{rpsg}];
+    for (uint r = 0u; r < {rpsg}u; ++r) acc[r] = 0.0f;
+    const float4 one4 = float4(1.0f);
+    for (uint t = 0u; t < {ntiles}u; ++t) {{
+        threadgroup_barrier(metal::mem_flags::mem_threadgroup);
+        for (uint cl = tid; cl < {tile}u; cl += {nthreads}u) {{
+            uint c = t * {tile}u + cl;
+            {stage}
+        }}
+        threadgroup_barrier(metal::mem_flags::mem_threadgroup);
+        for (uint i = lane * 4u; i < {tile}u; i += 128u) {{
+            float4 xv = *(const threadgroup float4*)(xb + i);
+            for (uint r = 0u; r < {rpsg}u; ++r) {{
+                char4 wv = *(const device char4*)((const device char*)W
+                            + (ulong)(row0 + r) * {rs}u + t * {tile}u + i);
+                acc[r] += metal::dot(float4(wv.x, wv.y, wv.z, wv.w) * xv, one4);
+            }}
+        }}
+    }}
+    for (uint r = 0u; r < {rpsg}u; ++r) {{
+        float a = metal::simd_sum(acc[r]);
+        if (lane == 0u) out[row0 + r] = scale[row0 + r] * a;
+    }}
+"""
+
+
+def get_s8_gemv_v3(rows, cols, rs, fuse_norm=False, eps=1e-6):
+    key = ("s8v3", rows, cols, rs, fuse_norm, round(eps, 12))
+    if key in _CACHE:
+        return _CACHE[key]
+    inputs = ["W", "scale", "x"]
+    if fuse_norm:
+        inputs.append("nw")
+    src = _s8_source_v3(rows, cols, rs, SG_PER_TG, fuse_norm, eps)
+    k = mx.fast.metal_kernel(name="s8gemv3_r%d_c%d_n%d" % (rows, cols, fuse_norm),
+                             input_names=inputs, output_names=["out"], source=src)
+    _CACHE[key] = (k, inputs)
+    return _CACHE[key]
+
+
+def s8_gemv_v3(W, scale, x, norm_w=None, eps=1e-6, stream=None):
+    """drop-in for trit_kernels.s8_gemv where rows % 64 == 0."""
+    rows, rs = W.shape
+    cols = x.shape[0]
+    k, names = get_s8_gemv_v3(rows, cols, rs, norm_w is not None, eps)
+    vals = {"W": W, "scale": scale, "x": x, "nw": norm_w}
+    nsg = rows // 8
+    ntg = (nsg + SG_PER_TG - 1) // SG_PER_TG
+    return k(inputs=[vals[n] for n in names],
+             grid=(ntg * SG_PER_TG * 32, 1, 1), threadgroup=(SG_PER_TG * 32, 1, 1),
+             output_shapes=[(rows,)], output_dtypes=[mx.float32], stream=stream)[0]
+
+
+def get_qknorm_rope_append(n_heads, n_kv, hd, maxseq, eps):
+    key = ("qkra", n_heads, n_kv, hd, maxseq, round(eps, 12))
+    if key in _CACHE:
+        return _CACHE[key]
+    h2 = hd // 2
+    nheads_total = n_heads + 2 * n_kv
+    src = f"""
+    uint tid  = thread_position_in_threadgroup.x;
+    uint lane = tid & 31u;
+    uint sg   = tid >> 5u;
+    uint head = threadgroup_position_in_grid.x * {SG_PER_TG}u + sg;
+    if (head >= {nheads_total}u) return;
+    uint pos = (uint)posbuf[0];
+    if (head == 0u && lane == 0u) {{ ((device float*)mask)[pos] = 0.0f; }}
+    device float* kc_w = (device float*)kc;
+    device float* vc_w = (device float*)vc;
+    if (head < {n_heads + n_kv}u) {{
+        uint base = head * {hd}u;
+        const device float* g = (head < {n_heads}u) ? qn : kn;
+        float ssq = 0.0f;
+        for (uint d = lane; d < {hd}u; d += 32u) {{
+            float v = qkv[base + d];
+            ssq = metal::fma(v, v, ssq);
+        }}
+        ssq = metal::simd_sum(ssq);
+        float rms = metal::rsqrt(ssq / {float(hd)}f + {eps:.9g}f);
+        for (uint d = lane; d < {hd}u; d += 32u) {{
+            float c  = ct[pos * {h2}u + (d % {h2}u)];
+            float sn = st[pos * {h2}u + (d % {h2}u)];
+            float v  = qkv[base + d] * rms * g[d];
+            float vr = (d < {h2}u)
+                     ? -(qkv[base + d + {h2}u] * rms * g[d + {h2}u])
+                     :  (qkv[base + d - {h2}u] * rms * g[d - {h2}u]);
+            float r = metal::fma(v, c, vr * sn);
+            if (head < {n_heads}u) {{
+                qout[base + d] = r;
+            }} else {{
+                uint kh = head - {n_heads}u;
+                kc_w[(ulong)(kh * {maxseq}u + pos) * {hd}u + d] = r;
+            }}
+        }}
+    }} else {{
+        uint vh = head - {n_heads + n_kv}u;
+        for (uint d = lane; d < {hd}u; d += 32u) {{
+            vc_w[(ulong)(vh * {maxseq}u + pos) * {hd}u + d] =
+                qkv[{(n_heads + n_kv) * hd}u + vh * {hd}u + d];
+        }}
+    }}
+"""
+    k = mx.fast.metal_kernel(
+        name="qknorm_rope_append_%d_%d_%d" % (n_heads, n_kv, hd),
+        input_names=["qkv", "qn", "kn", "kc", "vc", "ct", "st", "posbuf", "mask"],
+        output_names=["qout"], source=src)
+    _CACHE[key] = k
+    return k
+
+
+def qknorm_rope_append(qkv, qn, kn, kc, vc, ct, st, posbuf, mask,
+                       n_heads, n_kv, hd, maxseq, eps, stream=None):
+    """qkv fp32 [(n_heads+2*n_kv)*hd] -> roped+normed q fp32 [n_heads*hd];
+    writes normed+roped k and raw v into kc/vc at position posbuf[0] and
+    zeroes mask[pos]."""
+    k = get_qknorm_rope_append(n_heads, n_kv, hd, maxseq, eps)
+    nheads_total = n_heads + 2 * n_kv
+    ntg = (nheads_total + SG_PER_TG - 1) // SG_PER_TG
+    return k(inputs=[qkv, qn, kn, kc, vc, ct, st, posbuf, mask],
+             grid=(ntg * SG_PER_TG * 32, 1, 1), threadgroup=(SG_PER_TG * 32, 1, 1),
+             output_shapes=[(n_heads * hd,)], output_dtypes=[mx.float32],
+             stream=stream)[0]

mlx/fermion_mlx/container.py

@@ -0,0 +1,143 @@
+#!/usr/bin/env python3
+"""TRTC v4 arch-3 (Qwen3) container reader — numpy memmap views, zero-copy
+until the caller materializes.
+
+Layout (ground truth: scripts/export_trit_c_model.py; cross-checks:
+scripts/expand_trtc_v4_to_hf.py and kernels/gpu_e2e/runtime8b.py):
+  60 B header <Iii9i2fi>: magic 'TRTC', version=4, arch=3, n_layers, hidden,
+    n_heads, n_kv_heads, head_dim, rotary_dims, intermediate, vocab, max_pos,
+    f32 rms_norm_eps, f32 rope_theta, i32 embed_out_kind (eok)
+  eok=2 (untied, 8B): int8 embed_in record right after the header
+  per layer: input_layernorm f32[H], post_attention_layernorm f32[H],
+    q_norm f32[head_dim], k_norm f32[head_dim],
+    then 7 trit records (q,k,v,o,gate,up,down) — arch-3 QKV are bias-less
+  final norm f32[H]
+  int8 embed_out (lm_head) record; eok=1 (tied, 0.6B) derives embed_in
+    from this record.
+  trit record: i32 rows, cols, cols_pad, row_stride(bytes);
+    u8 bp/bn/br [rows*row_stride] LSB-first; f32 s_lo[rows], s_hi[rows];
+    i32 rs_lo[rows], rs_hi[rows] (skipped); i32 has_bias (+ f32 bias[rows])
+  int8 record: i32 rows, cols, cols_pad, row_stride (== cols_pad);
+    s8 W[rows*row_stride]; f32 scale[rows]; i32 wsum[rows] (skipped)
+
+Weight semantics: w[r,c] = (bp-bn) * (s_hi[r] if br else s_lo[r]);
+int8 embeds: w[r,c] = scale[r] * Q[r,c].
+"""
+import struct
+
+import numpy as np
+
+MAGIC = 0x43545254
+HDR_FMT = "<Iii9i2fi"
+HDR_BYTES = struct.calcsize(HDR_FMT)  # 60
+PROJS = ("q", "k", "v", "o", "gate", "up", "down")
+
+
+class TritRecord:
+    __slots__ = ("rows", "cols", "cols_pad", "row_stride", "bp", "bn", "br",
+                 "slo", "shi", "bias")
+
+
+class Int8Record:
+    __slots__ = ("rows", "cols", "cols_pad", "row_stride", "W", "scale")
+
+
+class Container:
+    pass
+
+
+def _trit_record(mm, off):
+    r = TritRecord()
+    r.rows, r.cols, r.cols_pad, r.row_stride = (
+        int(v) for v in np.frombuffer(mm, np.int32, 4, off))
+    off += 16
+    n = r.rows * r.row_stride
+    r.bp = np.frombuffer(mm, np.uint8, n, off).reshape(r.rows, r.row_stride); off += n
+    r.bn = np.frombuffer(mm, np.uint8, n, off).reshape(r.rows, r.row_stride); off += n
+    r.br = np.frombuffer(mm, np.uint8, n, off).reshape(r.rows, r.row_stride); off += n
+    r.slo = np.frombuffer(mm, np.float32, r.rows, off); off += 4 * r.rows
+    r.shi = np.frombuffer(mm, np.float32, r.rows, off); off += 4 * r.rows
+    off += 8 * r.rows  # rs_lo, rs_hi trit-sum sidecars (integrity data, unused here)
+    has_bias = int(np.frombuffer(mm, np.int32, 1, off)[0]); off += 4
+    r.bias = None
+    if has_bias:
+        r.bias = np.frombuffer(mm, np.float32, r.rows, off); off += 4 * r.rows
+    return r, off
+
+
+def _int8_record(mm, off):
+    r = Int8Record()
+    r.rows, r.cols, r.cols_pad, r.row_stride = (
+        int(v) for v in np.frombuffer(mm, np.int32, 4, off))
+    assert r.row_stride == r.cols_pad, "int8 record: row_stride must equal cols_pad"
+    off += 16
+    n = r.rows * r.row_stride
+    r.W = np.frombuffer(mm, np.int8, n, off).reshape(r.rows, r.row_stride); off += n
+    r.scale = np.frombuffer(mm, np.float32, r.rows, off); off += 4 * r.rows
+    off += 4 * r.rows  # wsum
+    return r, off
+
+
+def read_container(path):
+    """Memory-map a TRTC v4 arch-3 container; all arrays are views into the map."""
+    mm = np.memmap(path, dtype=np.uint8, mode="r")
+    h = struct.unpack(HDR_FMT, bytes(mm[:HDR_BYTES]))
+    c = Container()
+    (magic, c.version, c.arch, c.n_layers, c.hidden, c.n_heads, c.n_kv,
+     c.head_dim, c.rot, c.inter, c.vocab, c.maxpos, c.eps, c.theta, c.eok) = h
+    assert magic == MAGIC, f"bad magic {magic:#x}"
+    assert c.version == 4 and c.arch == 3, \
+        f"need TRTC v4 arch-3 (got v={c.version} arch={c.arch})"
+    assert c.eok in (1, 2), f"bad embed_out_kind {c.eok}"
+    off = HDR_BYTES
+    c.embed_in = None
+    if c.eok == 2:                      # untied: int8 embed_in follows the header
+        c.embed_in, off = _int8_record(mm, off)
+        assert (c.embed_in.rows, c.embed_in.cols) == (c.vocab, c.hidden)
+    H, hd = c.hidden, c.head_dim
+    q_dim, kv_dim = c.n_heads * hd, c.n_kv * hd
+    shapes = {"q": (q_dim, H), "k": (kv_dim, H), "v": (kv_dim, H),
+              "o": (H, q_dim), "gate": (c.inter, H), "up": (c.inter, H),
+              "down": (H, c.inter)}
+    c.layers = []
+    for li in range(c.n_layers):
+        L = {}
+        L["norm1"] = np.frombuffer(mm, np.float32, H, off); off += 4 * H
+        L["norm2"] = np.frombuffer(mm, np.float32, H, off); off += 4 * H
+        L["qnorm"] = np.frombuffer(mm, np.float32, hd, off); off += 4 * hd
+        L["knorm"] = np.frombuffer(mm, np.float32, hd, off); off += 4 * hd
+        for nm in PROJS:
+            L[nm], off = _trit_record(mm, off)
+            assert (L[nm].rows, L[nm].cols) == shapes[nm], \
+                f"L{li}.{nm}: {(L[nm].rows, L[nm].cols)} != {shapes[nm]}"
+            assert L[nm].bias is None, f"L{li}.{nm}: arch-3 records must be bias-less"
+        c.layers.append(L)
+    c.final_norm = np.frombuffer(mm, np.float32, H, off); off += 4 * H
+    c.embed_out, off = _int8_record(mm, off)
+    assert (c.embed_out.rows, c.embed_out.cols) == (c.vocab, c.hidden)
+    assert off == mm.size, f"reader ended at {off}, file is {mm.size}"
+    if c.embed_in is None:              # tied: same int8 record serves both
+        c.embed_in = c.embed_out
+    c.mm = mm                           # keep the map alive
+    return c
+
+
+# ---------------- fp32 reference math (gate-side, numpy) ----------------
+
+def unpack_plane(plane, cols):
+    return np.unpackbits(plane, axis=1, bitorder="little")[:, :cols]
+
+
+def dense_weights(rec, dtype=np.float32):
+    p = unpack_plane(rec.bp, rec.cols).astype(np.int8)
+    n = unpack_plane(rec.bn, rec.cols).astype(np.int8)
+    h = unpack_plane(rec.br, rec.cols)
+    s = (p - n).astype(dtype)
+    mag = np.where(h.astype(bool), rec.shi[:, None].astype(dtype),
+                   rec.slo[:, None].astype(dtype))
+    return s * mag
+
+
+def ref_rmsnorm(x, g, eps, dtype=np.float32):
+    x = x.astype(dtype)
+    return (x * (1.0 / np.sqrt(np.mean(x * x) + eps))) * g.astype(dtype)

mlx/fermion_mlx/gates.py

@@ -0,0 +1,164 @@
+#!/usr/bin/env python3
+"""House correctness gates for the MLX arch-3 path.
+
+refgate   : V1 gate (dspec runtime8b.py protocol) — teacher-forced logits +
+            greedy-with-resync vs the container's own fp expansion reference
+            npz {prompt_ids, tf_logits, greedy, meta}. Every argmax
+            divergence must be a near-tie <= tie_tol of the logit scale;
+            greedy flips resynced and bounded.
+cachegate : greedy-with-resync vs a banked hf_greedy_cache.json
+            (results_arch3_runtime format, keyed to container md5).
+pathgate  : path-consistency — the fused-kernel primary path and the pure
+            mx.fast-ops reference twin must produce the same greedy stream.
+
+All gates return (ok, receipt_dict); receipts carry per-flip absolute and
+relative margins so near-tie flips are documented, never waved through.
+"""
+import hashlib
+import json
+
+import mlx.core as mx
+import numpy as np
+
+
+def _md5(path):
+    h = hashlib.md5()
+    with open(path, "rb") as f:
+        while chunk := f.read(1 << 24):
+            h.update(chunk)
+    return h.hexdigest()
+
+
+def refgate(model, ref_path, tie_tol=0.04, max_flips=8):
+    ref = np.load(ref_path, allow_pickle=True)
+    ids = [int(t) for t in ref["prompt_ids"].tolist()]
+    tf = ref["tf_logits"]
+    greedy_ref = [int(t) for t in ref["greedy"].tolist()]
+    meta = json.loads(str(ref["meta"])) if "meta" in ref else {}
+    print(f"[refgate] prompt ids ({len(ids)}): {ids}")
+    print(f"[refgate] ref meta: {meta}")
+    rec = {"ref": str(ref_path), "meta": meta, "tf": [], "greedy_flips": [],
+           "tie_tol": tie_tol, "max_flips": max_flips}
+    # stage A: teacher-forced logits
+    mask = model.new_mask()
+    rels, ams, near, worst_gap = [], 0, 0, 0.0
+    for i, t in enumerate(ids):
+        _, _, lg = model.step(model.embed(t), i, mask)
+        g = np.array(lg, np.float64)
+        r = tf[i].astype(np.float64)
+        scale = float(np.abs(r).max())
+        rel = float(np.abs(g - r).max() / scale)
+        cos = float((g * r).sum() / (np.linalg.norm(g) * np.linalg.norm(r)))
+        gam, ram = int(g.argmax()), int(r.argmax())
+        am = gam == ram
+        ams += am
+        rels.append(rel)
+        extra = ""
+        if not am:
+            gap = float(g[gam] - g[ram]) / scale
+            worst_gap = max(worst_gap, gap)
+            near += gap <= tie_tol
+            extra = f" gap {100*gap:.3f}% ({'near-tie' if gap <= tie_tol else 'REAL'})"
+        rec["tf"].append({"pos": i, "rel": rel, "cos": cos, "argmax_match": am})
+        print(f"  pos {i:2d}: rel {100*rel:6.3f}% | cos {cos:.6f} | argmax "
+              f"{'match' if am else 'MISMATCH'} (mlx {gam} ref {ram}){extra}")
+    print(f"[refgate] stage A: TF rel max {100*max(rels):.3f}% / mean "
+          f"{100*float(np.mean(rels)):.3f}%, argmax {ams}/{len(ids)} "
+          f"(+{near} near-tie), worst gap {100*worst_gap:.3f}%")
+    rec["tf_summary"] = {"rel_max": max(rels), "rel_mean": float(np.mean(rels)),
+                         "argmax": f"{ams}/{len(ids)}", "near_tie": near}
+    # stage B: greedy with resync
+    mask = model.new_mask()
+    x, pos0 = model.prefill(ids, mask, compiled=False)
+    flips, g_toks, ok = 0, [], True
+    for s in range(len(greedy_ref)):
+        _, _, lg = model.step(x, pos0 + s, mask)
+        l = np.array(lg, np.float64)
+        g_tok = int(l.argmax())
+        g_toks.append(g_tok)
+        tok = g_tok
+        if g_tok != greedy_ref[s]:
+            gap_abs = float(l[g_tok] - l[greedy_ref[s]])
+            scale = float(np.abs(l).max())
+            gap = gap_abs / scale
+            flips += 1
+            worst_gap = max(worst_gap, gap)
+            rec["greedy_flips"].append({"step": s, "mlx": g_tok,
+                                        "ref": greedy_ref[s],
+                                        "margin_abs_logits": gap_abs,
+                                        "margin_rel": gap})
+            print(f"  step {s}: mlx {g_tok} vs ref {greedy_ref[s]}, gap "
+                  f"{gap_abs:.4f} logits = {100*gap:.3f}% of scale -> resync")
+            if flips > max_flips:
+                ok = False
+                break
+            tok = greedy_ref[s]
+        x = model.embed(tok)
+        mx.eval(x)
+    print(f"[refgate] ref greedy: {greedy_ref}")
+    print(f"[refgate] mlx greedy: {g_toks}")
+    ok = ok and worst_gap <= tie_tol and flips <= max_flips
+    rec.update(flips=flips, worst_gap=worst_gap, ok=bool(ok),
+               mlx_greedy=g_toks, ref_greedy=greedy_ref)
+    print(f"[refgate] {'PASS' if ok else 'FAIL'} (worst gap {100*worst_gap:.3f}% "
+          f"tol {100*tie_tol:.1f}%; {flips} flips, tol {max_flips})")
+    return ok, rec
+
+
+def cachegate(model, container_path, cache_path, tie_tol=0.04, max_flips=8):
+    cache = json.load(open(cache_path))
+    md5 = _md5(container_path)
+    print(f"[cachegate] container md5 {md5} vs cache key {cache['container_md5']}")
+    assert md5 == cache["container_md5"], "cache is for a different container"
+    rec = {"cache": str(cache_path), "container_md5": md5, "prompts": [],
+           "tie_tol": tie_tol, "max_flips_per_prompt": max_flips}
+    ok = True
+    tot_flips, worst = 0, 0.0
+    for pi, (prompt, ref) in enumerate(zip(cache["prompts"], cache["tokens"])):
+        mask = model.new_mask()
+        x, pos0 = model.prefill([int(t) for t in prompt], mask)
+        flips, fliprec = 0, []
+        for s, rt in enumerate(ref):
+            _, _, lg = model.step(x, pos0 + s, mask)
+            l = np.array(lg, np.float64)
+            g_tok = int(l.argmax())
+            tok = g_tok
+            if g_tok != int(rt):
+                gap_abs = float(l[g_tok] - l[int(rt)])
+                gap = gap_abs / float(np.abs(l).max())
+                worst = max(worst, gap)
+                flips += 1
+                fliprec.append({"step": s, "mlx": g_tok, "ref": int(rt),
+                                "margin_abs_logits": gap_abs, "margin_rel": gap})
+                print(f"  p{pi} step {s}: mlx {g_tok} vs hf {rt}, gap "
+                      f"{gap_abs:.4f} logits = {100*gap:.3f}% -> resync")
+                tok = int(rt)
+            x = model.embed(tok)
+            mx.eval(x)
+        tot_flips += flips
+        good = flips <= max_flips
+        ok = ok and good
+        rec["prompts"].append({"prompt": prompt, "steps": len(ref),
+                               "flips": flips, "flip_detail": fliprec,
+                               "pass": bool(good)})
+        print(f"  prompt {pi}: {len(ref)} steps, {flips} resynced flips -> "
+              f"{'PASS' if good else 'FAIL'}")
+    ok = ok and worst <= tie_tol
+    rec.update(total_flips=tot_flips, worst_gap=worst, ok=bool(ok))
+    print(f"[cachegate] {'PASS' if ok else 'FAIL'} ({tot_flips} flips total, "
+          f"worst gap {100*worst:.3f}% tol {100*tie_tol:.1f}%)")
+    return ok, rec
+
+
+def pathgate(model, ids, n=32):
+    """fused-kernel path vs pure-mx.fast-ops twin: greedy streams must be
+    IDENTICAL (same weights, same GEMV kernels; isolates the new kernel)."""
+    fused, _ = model.generate(ids, n, compiled=True)
+    ref = model.generate_ref(ids, n)
+    same = fused == ref
+    d = next((i for i in range(min(len(fused), len(ref)))
+              if fused[i] != ref[i]), None)
+    print(f"[pathgate] fused-vs-mxops {n}-token greedy: "
+          f"{'IDENTICAL' if same else f'FIRST DIVERGENCE at {d}'}")
+    return same, {"n": n, "identical": bool(same), "first_divergence": d,
+                  "fused": fused, "mxops": ref}

mlx/fermion_mlx/mbatch.py

@@ -0,0 +1,164 @@
+#!/usr/bin/env python3
+"""Small-batch (M-token) GEMM kernels for speculative verify — EXPERIMENTAL.
+
+Why these exist: the shipped decode path is M=1 GEMV. Speculative decoding
+only wins if the verifier scores k+1 draft positions while streaming the
+weight planes ONCE; re-running the GEMV k+1 times re-reads the weights k+1
+times and cannot beat plain decode. These kernels keep the v5/v7 interleaved
+plane layout + one-weight-read structure and add an M-wide accumulator:
+
+  trit_gemm_m : five-value planes  X[M, cols] -> out[M, rows]
+                v7 lane mapping (lane = row(8) x word-slot(4), planes read
+                once, fully coalesced) + v6 mask-convert-FMA decode (float4
+                (uint4(a) & m4) == 2^bit when set; x pre-scaled by 2^-bit,
+                exact in fp32). No LUT: a per-token LUT tile for M=5 exceeds
+                the 32KB threadgroup budget at inter=12288.
+  s8_gemm_m   : int8 rows (lm_head / untied embeds), one simdgroup per row,
+                weight char4 loaded once and dotted against all M x-vectors.
+
+No norm/GLU/residual template flags here: the spec verify path applies
+RMSNorm / SwiGLU / residual adds as plain MLX elementwise ops on [M, ...]
+tensors (cheap at M<=8), keeping these kernels pure GEMMs.
+
+Additive module — nothing in trit_kernels.py / arch3.py / model.py changes.
+"""
+import mlx.core as mx
+
+SG_PER_TG = 8
+_CACHE = {}
+
+
+def _trit_gemm_m_source(M, rows, cols, rs):
+    assert rs % 4 == 0 and rs * 8 == cols and cols % 32 == 0 and rows % 8 == 0
+    W = rs // 4
+    kbody = []
+    for k in range(8):
+        m4 = [1 << (4 * k + i) for i in range(4)]
+        ps = ", ".join("%.9ef" % (2.0 ** -(4 * k + i)) for i in range(4))
+        loads = "\n".join(
+            f"""            {{
+                float4 xs = x4[{m}u * {cols // 4}u + wl * 8u + {k}u] * ps{k};
+                accLo[{m}] += metal::dot(sa, xs);
+                accHi[{m}] += metal::dot(sb, xs);
+            }}""" for m in range(M))
+        kbody.append(f"""        {{
+            const uint4 m4 = uint4({m4[0]}u, {m4[1]}u, {m4[2]}u, {m4[3]}u);
+            const float4 ps{k} = float4({ps});
+            float4 sa = float4(uint4(a) & m4) - float4(uint4(b) & m4);
+            float4 sb = float4(uint4(cc) & m4) - float4(uint4(d) & m4);
+{loads}
+        }}""")
+    kbody = "\n".join(kbody)
+    outs = "\n".join(
+        f"""        accLo[{m}] += metal::simd_shuffle_down(accLo[{m}], 16u);
+        accLo[{m}] += metal::simd_shuffle_down(accLo[{m}], 8u);
+        accHi[{m}] += metal::simd_shuffle_down(accHi[{m}], 16u);
+        accHi[{m}] += metal::simd_shuffle_down(accHi[{m}], 8u);"""
+        for m in range(M))
+    writes = "\n".join(
+        f"        out[{m}u * {rows}u + row] = "
+        f"metal::fma(slo[row], accLo[{m}], shi[row] * accHi[{m}]);"
+        for m in range(M))
+    return f"""
+    uint tid  = thread_position_in_threadgroup.x;
+    uint lane = tid & 31u;
+    uint sg   = tid >> 5u;
+    uint blk  = threadgroup_position_in_grid.x * {SG_PER_TG}u + sg;
+    uint row0 = blk * 8u;
+    if (row0 >= {rows}u) return;
+    uint r    = lane & 7u;
+    uint wsl  = lane >> 3u;
+    const device uint* p32 = (const device uint*)bp;
+    const device uint* n32 = (const device uint*)bn;
+    const device uint* h32 = (const device uint*)br;
+    const device float4* x4 = (const device float4*)x;
+    float accLo[{M}], accHi[{M}];
+    for (uint m = 0u; m < {M}u; ++m) {{ accLo[m] = 0.0f; accHi[m] = 0.0f; }}
+    for (uint wl = wsl; wl < {W}u; wl += 4u) {{
+        ulong base = ((ulong)blk * {W}u + wl) * 8u + r;
+        uint pw = p32[base], nw2 = n32[base], hw = h32[base];
+        uint a = pw & ~hw, b = nw2 & ~hw, cc = pw & hw, d = nw2 & hw;
+{kbody}
+    }}
+{outs}
+    if (lane < 8u) {{
+        uint row = row0 + lane;
+{writes}
+    }}
+"""
+
+
+def _s8_gemm_m_source(M, rows, cols, rs):
+    assert rs % 4 == 0 and cols % 4 == 0
+    accs = "\n".join(
+        f"        acc[{m}] += metal::dot(wf, x4[{m}u * {cols // 4}u + i]);"
+        for m in range(M))
+    reduces = "\n".join(
+        f"""    {{
+        float a = metal::simd_sum(acc[{m}]);
+        if (lane == 0u) out[{m}u * {rows}u + row] = scale[row] * a;
+    }}""" for m in range(M))
+    return f"""
+    uint tid  = thread_position_in_threadgroup.x;
+    uint lane = tid & 31u;
+    uint sg   = tid >> 5u;
+    uint row  = threadgroup_position_in_grid.x * {SG_PER_TG}u + sg;
+    if (row >= {rows}u) return;
+    const device char* w = (const device char*)W + (ulong)row * {rs}u;
+    const device float4* x4 = (const device float4*)x;
+    float acc[{M}];
+    for (uint m = 0u; m < {M}u; ++m) acc[m] = 0.0f;
+    for (uint i = lane; i < {cols // 4}u; i += 32u) {{
+        char4 wv = *(const device char4*)(w + i * 4u);
+        float4 wf = float4(wv.x, wv.y, wv.z, wv.w);
+{accs}
+    }}
+{reduces}
+"""
+
+
+def _get(kind, M, rows, cols, rs):
+    key = (kind, M, rows, cols, rs)
+    if key in _CACHE:
+        return _CACHE[key]
+    if kind == "trit":
+        src = _trit_gemm_m_source(M, rows, cols, rs)
+        k = mx.fast.metal_kernel(
+            name=f"tritgemm_m{M}_r{rows}_c{cols}",
+            input_names=["bp", "bn", "br", "slo", "shi", "x"],
+            output_names=["out"], source=src)
+    else:
+        src = _s8_gemm_m_source(M, rows, cols, rs)
+        k = mx.fast.metal_kernel(
+            name=f"s8gemm_m{M}_r{rows}_c{cols}",
+            input_names=["W", "scale", "x"],
+            output_names=["out"], source=src)
+    _CACHE[key] = k
+    return k
+
+
+def trit_gemm_m(planes, slo, shi, X, stream=None):
+    """planes v5-interleaved (KERNEL_VERSION>=5 prep). X fp32 [M, cols]
+    (already normed / activated). Returns fp32 [M, rows]."""
+    bp, bn, br = planes
+    rows, rs = bp.shape
+    M, cols = X.shape
+    k = _get("trit", M, rows, cols, rs)
+    nsg = rows // 8
+    ntg = (nsg + SG_PER_TG - 1) // SG_PER_TG
+    return k(inputs=[bp, bn, br, slo, shi, X],
+             grid=(ntg * SG_PER_TG * 32, 1, 1), threadgroup=(SG_PER_TG * 32, 1, 1),
+             output_shapes=[(M, rows)], output_dtypes=[mx.float32],
+             stream=stream)[0]
+
+
+def s8_gemm_m(W, scale, X, stream=None):
+    """int8 W [rows, rs], X fp32 [M, cols] (already normed). -> [M, rows]."""
+    rows, rs = W.shape
+    M, cols = X.shape
+    k = _get("s8", M, rows, cols, rs)
+    ntg = (rows + SG_PER_TG - 1) // SG_PER_TG
+    return k(inputs=[W, scale, X],
+             grid=(ntg * SG_PER_TG * 32, 1, 1), threadgroup=(SG_PER_TG * 32, 1, 1),
+             output_shapes=[(M, rows)], output_dtypes=[mx.float32],
+             stream=stream)[0]

mlx/fermion_mlx/model.py

@@ -0,0 +1,281 @@
+#!/usr/bin/env python3
+"""End-to-end MLX/Metal decode for TRTC v4 **arch-3 (Qwen3)** five-value
+containers — Neutrino-0.6B (tied int8 embeds) and Neutrino-8B (untied).
+
+Every transformer linear runs on the banked five-value {0,±s_lo,±s_hi}
+3-bit-planar Metal GEMV kernels (vendored trit_kernels.py, byte-identical
+to kernels/metal/trit_kernels.py): qkv / o / gate+up / down fused per layer
++ the int8 lm_head GEMV. The arch-3 delta — per-head Q/K-RMSNorm before
+rope, biasless qkv, int8 embed_in — is handled by the new fused
+qknorm_rope_append kernel (arch3.py) and an int8 embedding dequant.
+
+Fusions per decode token: rmsnorm folded into qkv/gu/lm_head GEMVs, SwiGLU
+folded into the down GEMV, residual adds folded into o/down epilogues,
+QK-norm+rope+KV-append in one dispatch. MLX supplies SDPA, argmax and the
+lazy-graph dispatch batching.
+
+Two forward implementations:
+  _step_fn  : primary path (fused kernel, preallocated KV + additive mask,
+              mx.compile-able) — the shipped/gated/benched path.
+  step_ref  : pure-MLX-ops reference twin for the NEW kernel (mx.fast
+              rms_norm/rope, concat KV) — used by the path-consistency gate.
+"""
+import time
+
+import mlx.core as mx
+import numpy as np
+
+from .container import read_container
+from .trit_kernels import trit_gemv, s8_gemv, prep_planes
+from . import trit_kernels
+from .arch3 import qknorm_rope_append, s8_gemv_v3
+
+NEG_INF = -1e9
+
+
+class _Layer:
+    pass
+
+
+def _cat(arrs):
+    return np.ascontiguousarray(np.concatenate(arrs, axis=0))
+
+
+class MetalTritQwen3:
+    """TRTC v4 arch-3 walker (0.6B or 8B, dims from the container header)."""
+
+    def __init__(self, path, maxseq=1024, verbose=True):
+        t0 = time.time()
+        c = read_container(path)
+        self.meta = c
+        self.eps, self.theta = float(c.eps), float(c.theta)
+        self.n_layers, self.hidden = c.n_layers, c.hidden
+        self.n_heads, self.n_kv, self.hd = c.n_heads, c.n_kv, c.head_dim
+        self.inter, self.vocab, self.eok = c.inter, c.vocab, c.eok
+        assert c.rot == self.hd, "kernels assume full-head_dim rope"
+        self.scale = self.hd ** -0.5
+        self.qd = self.n_heads * self.hd
+        self.kd = self.n_kv * self.hd
+        self.maxseq = maxseq
+
+        # int8 lm_head (+ tied/untied int8 embed_in)
+        eo = c.embed_out
+        self.eoW = mx.array(np.ascontiguousarray(eo.W))          # int8 [V, H]
+        self.eo_scale = mx.array(np.ascontiguousarray(eo.scale))
+        mx.eval(self.eoW, self.eo_scale)
+        if c.eok == 2:
+            ei = c.embed_in
+            self.embW = mx.array(np.ascontiguousarray(ei.W))     # int8 [V, H]
+            self.embS = mx.array(np.ascontiguousarray(ei.scale))
+            mx.eval(self.embW, self.embS)
+        else:
+            self.embW, self.embS = self.eoW, self.eo_scale
+
+        self.layers = []
+        for L in c.layers:
+            q, k, v, o, gate, up, down = (L[n] for n in
+                                          ("q", "k", "v", "o", "gate", "up", "down"))
+            y = _Layer()
+            y.norm1 = mx.array(np.ascontiguousarray(L["norm1"]))
+            y.norm2 = mx.array(np.ascontiguousarray(L["norm2"]))
+            y.qnorm = mx.array(np.ascontiguousarray(L["qnorm"]))
+            y.knorm = mx.array(np.ascontiguousarray(L["knorm"]))
+            y.qkv_planes = prep_planes(tuple(
+                mx.array(_cat([getattr(r, pl) for r in (q, k, v)]))
+                for pl in ("bp", "bn", "br")), q.cols)
+            y.qkv_slo = mx.array(_cat([q.slo, k.slo, v.slo]))
+            y.qkv_shi = mx.array(_cat([q.shi, k.shi, v.shi]))
+            y.o_planes = prep_planes(tuple(
+                mx.array(np.ascontiguousarray(getattr(o, pl)))
+                for pl in ("bp", "bn", "br")), o.cols)
+            y.o_slo = mx.array(np.ascontiguousarray(o.slo))
+            y.o_shi = mx.array(np.ascontiguousarray(o.shi))
+            y.gu_planes = prep_planes(tuple(
+                mx.array(_cat([getattr(gate, pl), getattr(up, pl)]))
+                for pl in ("bp", "bn", "br")), gate.cols)
+            y.gu_slo = mx.array(_cat([gate.slo, up.slo]))
+            y.gu_shi = mx.array(_cat([gate.shi, up.shi]))
+            y.dn_planes = prep_planes(tuple(
+                mx.array(np.ascontiguousarray(getattr(down, pl)))
+                for pl in ("bp", "bn", "br")), down.cols)
+            y.dn_slo = mx.array(np.ascontiguousarray(down.slo))
+            y.dn_shi = mx.array(np.ascontiguousarray(down.shi))
+            mx.eval(*(y.qkv_planes + y.o_planes + y.gu_planes + y.dn_planes),
+                    y.qkv_slo, y.qkv_shi, y.o_slo, y.o_shi,
+                    y.gu_slo, y.gu_shi, y.dn_slo, y.dn_shi,
+                    y.norm1, y.norm2, y.qnorm, y.knorm)
+            self.layers.append(y)
+        self.final_norm = mx.array(np.ascontiguousarray(c.final_norm))
+
+        # rope tables + preallocated KV + mask
+        inv = self.theta ** -(np.arange(0, self.hd, 2, dtype=np.float64) / self.hd)
+        ang = np.outer(np.arange(maxseq, dtype=np.float64), inv)
+        self.ct = mx.array(np.cos(ang).astype(np.float32).ravel())
+        self.st = mx.array(np.sin(ang).astype(np.float32).ravel())
+        self.kc = [mx.zeros((self.n_kv, maxseq, self.hd), dtype=mx.float32)
+                   for _ in self.layers]
+        self.vc = [mx.zeros((self.n_kv, maxseq, self.hd), dtype=mx.float32)
+                   for _ in self.layers]
+        mx.eval(self.ct, self.st, self.final_norm, *self.kc, *self.vc)
+        self._stepc = None
+        # x-restaged int8 unembed when the row count allows it
+        self._s8 = s8_gemv_v3 if self.vocab % 64 == 0 else s8_gemv
+        if verbose:
+            gb = mx.get_active_memory() / 2**30
+            print(f"loaded {path} in {time.time()-t0:.1f}s (arch-3, "
+                  f"{self.n_layers}L/{self.hidden}H/{self.n_heads}q/{self.n_kv}kv/"
+                  f"{self.inter}i/{self.vocab}V eok={self.eok}, kernel v"
+                  f"{trit_kernels.KERNEL_VERSION}, maxseq {maxseq}, "
+                  f"active mem {gb:.2f} GiB)")
+
+    # ---------------- primary path ----------------
+
+    def new_mask(self):
+        m = mx.full((self.maxseq,), NEG_INF, dtype=mx.float32)
+        mx.eval(m)
+        return m
+
+    def embed(self, tok):
+        """int8 embedding dequant: fp32 row = scale[tok] * W8[tok]."""
+        return self.embW[tok].astype(mx.float32) * self.embS[tok]
+
+    def _window(self, pos):
+        """KV window for position pos: grown in 256-slot blocks. Slicing off
+        the -1e9-masked tail is numerically exact (exp underflows to 0.0 in
+        fp32), so shrinking the SDPA read never changes the math — it only
+        stops streaming megabytes of masked cache per step."""
+        return min(self.maxseq, ((pos + 1 + 255) // 256) * 256)
+
+    def _step_fn(self, x, posbuf, mask, W):
+        """x fp32 [H] at position posbuf[0] -> (next_tok, x_next, logits).
+        Fixed shapes per W: SDPA over the first W cache slots with additive
+        mask (stale slots -1e9; qknorm_rope_append maintains mask[pos]=0)."""
+        eps = self.eps
+        m4 = mask[:W].reshape(1, 1, 1, W)
+        for li, L in enumerate(self.layers):
+            qkv = trit_gemv(L.qkv_planes, L.qkv_slo, L.qkv_shi, x,
+                            norm_w=L.norm1, eps=eps)
+            q = qknorm_rope_append(qkv, L.qnorm, L.knorm, self.kc[li], self.vc[li],
+                                   self.ct, self.st, posbuf, mask,
+                                   self.n_heads, self.n_kv, self.hd,
+                                   self.maxseq, eps)
+            q = q.reshape(1, self.n_heads, 1, self.hd)
+            a = mx.fast.scaled_dot_product_attention(
+                q, self.kc[li][:, :W][None], self.vc[li][:, :W][None],
+                scale=self.scale, mask=m4)
+            a = a.reshape(self.qd)
+            x = trit_gemv(L.o_planes, L.o_slo, L.o_shi, a, resid=x, eps=eps)
+            gu = trit_gemv(L.gu_planes, L.gu_slo, L.gu_shi, x,
+                           norm_w=L.norm2, eps=eps)
+            x = trit_gemv(L.dn_planes, L.dn_slo, L.dn_shi, gu, glu=True,
+                          resid=x, eps=eps)
+        logits = self._s8(self.eoW, self.eo_scale, x, norm_w=self.final_norm, eps=eps)
+        nt = mx.argmax(logits)
+        return nt, self.embed(nt), logits
+
+    def step(self, x, pos, mask):
+        """uncompiled single step (gates)."""
+        return self._step_fn(x, mx.array([pos], dtype=mx.int32), mask,
+                             self._window(pos))
+
+    def step_compiled(self, x, posbuf, mask, W):
+        if self._stepc is None:
+            self._stepc = {}
+        if W not in self._stepc:
+            self._stepc[W] = mx.compile(
+                lambda xx, pb, mk, _W=W: self._step_fn(xx, pb, mk, _W))
+        return self._stepc[W](x, posbuf, mask)
+
+    def prefill(self, ids, mask, compiled=True):
+        """feed ids[:-1]; returns (x armed with ids[-1], pos of ids[-1])."""
+        for i, t in enumerate(ids[:-1]):
+            pb = mx.array([i], dtype=mx.int32)
+            W = self._window(i)
+            if compiled:
+                nt, xn, lg = self.step_compiled(self.embed(int(t)), pb, mask, W)
+            else:
+                nt, xn, lg = self._step_fn(self.embed(int(t)), pb, mask, W)
+            mx.eval(lg)
+        x = self.embed(int(ids[-1]))
+        mx.eval(x)
+        return x, len(ids) - 1
+
+    def generate(self, ids, n, compiled=True, eos=None):
+        """greedy decode n tokens after prompt ids; returns (tokens,
+        decode_seconds). eos: optional set of stop ids (stop AFTER emitting)."""
+        mask = self.new_mask()
+        x, pos0 = self.prefill(ids, mask, compiled=compiled)
+        toks = []
+        prev = None
+        t0 = time.perf_counter()
+        for i in range(n):
+            pos = pos0 + i
+            pb = mx.array([pos], dtype=mx.int32)
+            W = self._window(pos)
+            if compiled:
+                nt, x, lg = self.step_compiled(x, pb, mask, W)
+            else:
+                nt, x, lg = self._step_fn(x, pb, mask, W)
+            mx.async_eval(nt, x)
+            if prev is not None:
+                toks.append(int(prev))
+                if eos and toks[-1] in eos:
+                    prev = None
+                    break
+            prev = nt
+        if prev is not None:
+            toks.append(int(prev))
+        mx.eval(x)
+        dt = time.perf_counter() - t0
+        return toks, dt
+
+    # ---------------- pure-MLX-ops reference twin ----------------
+
+    def step_ref(self, x, kv, pos):
+        """same GEMV kernels, but QK-norm/rope/cache via mx.fast ops +
+        concat KV — the cross-check for the NEW fused kernel."""
+        eps = self.eps
+        for li, L in enumerate(self.layers):
+            qkv = trit_gemv(L.qkv_planes, L.qkv_slo, L.qkv_shi, x,
+                            norm_w=L.norm1, eps=eps)
+            q = mx.fast.rms_norm(qkv[:self.qd].reshape(self.n_heads, self.hd),
+                                 L.qnorm, eps)
+            k = mx.fast.rms_norm(qkv[self.qd:self.qd + self.kd]
+                                 .reshape(self.n_kv, self.hd), L.knorm, eps)
+            qk = mx.concatenate([q, k], axis=0).reshape(
+                1, self.n_heads + self.n_kv, 1, self.hd)
+            qk = mx.fast.rope(qk, self.hd, traditional=False, base=self.theta,
+                              scale=1.0, offset=pos)
+            qh = qk[:, :self.n_heads]
+            kh = qk[:, self.n_heads:]
+            vh = qkv[self.qd + self.kd:].reshape(1, self.n_kv, 1, self.hd)
+            if kv[li] is None:
+                kv[li] = (kh, vh)
+            else:
+                kv[li] = (mx.concatenate([kv[li][0], kh], axis=2),
+                          mx.concatenate([kv[li][1], vh], axis=2))
+            keys, values = kv[li]
+            a = mx.fast.scaled_dot_product_attention(qh, keys, values,
+                                                     scale=self.scale)
+            a = a.reshape(self.qd)
+            x = trit_gemv(L.o_planes, L.o_slo, L.o_shi, a, resid=x, eps=eps)
+            gu = trit_gemv(L.gu_planes, L.gu_slo, L.gu_shi, x,
+                           norm_w=L.norm2, eps=eps)
+            x = trit_gemv(L.dn_planes, L.dn_slo, L.dn_shi, gu, glu=True,
+                          resid=x, eps=eps)
+        return self._s8(self.eoW, self.eo_scale, x, norm_w=self.final_norm, eps=eps)
+
+    def generate_ref(self, ids, n):
+        kv = [None] * self.n_layers
+        for i, t in enumerate(ids[:-1]):
+            lg = self.step_ref(self.embed(int(t)), kv, i)
+            mx.eval(lg)
+        x = self.embed(int(ids[-1]))
+        toks = []
+        for i in range(n):
+            lg = self.step_ref(x, kv, len(ids) - 1 + i)
+            nt = mx.argmax(lg)
+            x = self.embed(nt)
+            mx.eval(x)
+            toks.append(int(nt))
+        return toks

mlx/fermion_mlx/spec.py

@@ -0,0 +1,256 @@
+#!/usr/bin/env python3
+"""EXPERIMENTAL speculative decoding: 0.6B pack drafts, 8B pack verifies.
+
+House exactness rule (greedy-exact acceptance): a draft token is accepted
+iff it equals the verifier's argmax at that position. The emitted stream is
+therefore exactly the verifier's own greedy stream *as computed by the
+batched verify path* — the ship gate (specgate) checks that stream is
+token-identical to the shipped single-token path at 32 and 256 tokens.
+
+Mechanics per round (k=4 draft tokens, M=k+1 verify batch):
+  1. draft consumes its pending tokens, then chains k greedy proposals
+     d_1..d_k on its own single-token path;
+  2. verifier scores [pending[-1], d_1..d_k] in ONE batched pass
+     (mbatch.trit_gemm_m / s8_gemm_m — weight planes stream once, which is
+     the entire speedup mechanism on a bandwidth-bound GPU);
+  3. accept the longest prefix with d_i == argmax_{i-1}; emit accepted
+     tokens + the verifier's own next token (correction or bonus);
+  4. KV rewind: positions are the source of truth. The verifier's stale
+     rows get overwritten by the next round's appends before any read (the
+     verify mask only allows slots <= row position). The draft re-masks its
+     stale slots (additive mask back to -1e9) and rolls its position back.
+
+Both models live in one process; run under --mem-limit-gb 6 (house OOM
+rule). Additive module: model.py / gates.py / existing CLI modes untouched.
+"""
+import json
+import time
+
+import mlx.core as mx
+
+from .mbatch import trit_gemm_m, s8_gemm_m
+
+NEG_INF = -1e9
+
+
+def _silu(g):
+    return g * mx.sigmoid(g)
+
+
+class SpecDecoder:
+    def __init__(self, verifier, draft, k=4):
+        assert verifier.vocab == draft.vocab, "draft/verifier vocab mismatch"
+        self.V, self.D, self.k = verifier, draft, k
+        self._vc = {}                    # compiled verify fns keyed (M, W)
+        self._specmask = verifier.new_mask()   # kernel side-channel, never read
+        self.stats = None
+
+    # ---------------- batched verify ----------------
+
+    def _verify(self, toks, pos0):
+        from .arch3 import qknorm_rope_append
+        V = self.V
+        M = len(toks)
+        W = V._window(pos0 + M - 1)
+        key = (M, W)
+        if key not in self._vc:
+            # build an uncompiled closure once; mx.compile wrapper around it
+            eps = V.eps
+
+            def fn(X, pbs, amask, _M=M, _W=W):
+                m4 = amask.reshape(1, 1, _M, _W)
+                for li, L in enumerate(V.layers):
+                    qkv = trit_gemm_m(L.qkv_planes, L.qkv_slo, L.qkv_shi,
+                                      mx.fast.rms_norm(X, L.norm1, eps))
+                    qrows = [qknorm_rope_append(
+                        qkv[m], L.qnorm, L.knorm, V.kc[li], V.vc[li],
+                        V.ct, V.st, pbs[m:m + 1], self._specmask,
+                        V.n_heads, V.n_kv, V.hd, V.maxseq, eps)
+                        for m in range(_M)]
+                    q = mx.stack(qrows).reshape(_M, V.n_heads, V.hd)
+                    q = q.transpose(1, 0, 2)[None]
+                    a = mx.fast.scaled_dot_product_attention(
+                        q, V.kc[li][:, :_W][None], V.vc[li][:, :_W][None],
+                        scale=V.scale, mask=m4)
+                    a = a[0].transpose(1, 0, 2).reshape(_M, V.qd)
+                    X = X + trit_gemm_m(L.o_planes, L.o_slo, L.o_shi, a)
+                    gu = trit_gemm_m(L.gu_planes, L.gu_slo, L.gu_shi,
+                                     mx.fast.rms_norm(X, L.norm2, eps))
+                    h = _silu(gu[:, :V.inter]) * gu[:, V.inter:]
+                    X = X + trit_gemm_m(L.dn_planes, L.dn_slo, L.dn_shi, h)
+                logits = s8_gemm_m(V.eoW, V.eo_scale,
+                                   mx.fast.rms_norm(X, V.final_norm, eps))
+                return mx.argmax(logits, axis=1)
+
+            self._vc[key] = mx.compile(fn)
+        tarr = mx.array(toks, dtype=mx.int32)
+        X = V.embW[tarr].astype(mx.float32) * V.embS[tarr][:, None]
+        pbs = mx.array([pos0 + m for m in range(M)], dtype=mx.int32)
+        idx = mx.arange(W)[None, :]
+        rowp = (pos0 + mx.arange(M))[:, None]
+        amask = mx.where(idx <= rowp, mx.array(0.0, dtype=mx.float32),
+                         mx.array(NEG_INF, dtype=mx.float32))
+        am = self._vc[(M, W)](X, pbs, amask)
+        mx.eval(am)
+        return [int(t) for t in am]
+
+    # ---------------- draft helpers (single-token path) ----------------
+
+    def _draft_chain(self, pending, dmask, dpos):
+        """consume pending tokens, then chain k greedy proposals.
+        Returns (proposals, new_dpos). Draft KV/mask advance by
+        len(pending) + k - 1 consumed inputs."""
+        # NOTE: each step is dispatched with async_eval before the next is
+        # built — the KV/mask writes are input mutations invisible to the
+        # lazy graph, and batching several steps into one evaluation makes
+        # MLX copy-on-write the caches and silently drop intermediate
+        # appends (found the hard way; the shipped generate() uses the same
+        # per-step dispatch discipline).
+        D, k = self.D, self.k
+        pos = dpos
+        nt = x = None
+        for t in pending:
+            pb = mx.array([pos], dtype=mx.int32)
+            nt, x, _ = D.step_compiled(D.embed(int(t)), pb, dmask,
+                                       D._window(pos))
+            mx.async_eval(nt, x)
+            pos += 1
+        props = [nt]                           # d_1
+        for _ in range(k - 1):
+            pb = mx.array([pos], dtype=mx.int32)
+            nt, x, _ = D.step_compiled(x, pb, dmask, D._window(pos))
+            mx.async_eval(nt, x)
+            props.append(nt)
+            pos += 1
+        mx.eval(*props)
+        return [int(p) for p in props], pos
+
+    # ---------------- main loop ----------------
+
+    def generate(self, ids, n):
+        """greedy spec decode: n tokens after prompt ids.
+        Returns (tokens, decode_seconds, stats)."""
+        V, D, k = self.V, self.D, self.k
+        vmask = V.new_mask()
+        dmask = D.new_mask()
+        _, p0 = V.prefill(ids, vmask)
+        _, _ = D.prefill(ids, dmask)
+        # both consumed ids[:-1]; next input ids[-1] at position p0
+        pending = [int(ids[-1])]
+        vpos = dpos = p0
+        toks = []
+        rounds = accepted = proposed = 0
+        hist = [0] * (k + 1)
+        t0 = time.perf_counter()
+        while len(toks) < n:
+            # invariant: pending[-1] sits at position vpos for the verifier
+            # and at dpos + len(pending) - 1 for the draft — same slot.
+            assert dpos + len(pending) - 1 == vpos, (dpos, len(pending), vpos)
+            props, dpos_after = self._draft_chain(pending, dmask, dpos)
+            am = self._verify([pending[-1]] + props, vpos)
+            nacc = 0
+            for i in range(k):
+                if props[i] == am[i]:
+                    nacc += 1
+                else:
+                    break
+            rounds += 1
+            proposed += k
+            accepted += nacc
+            hist[nacc] += 1
+            base = vpos                          # position of pending[-1]
+            if nacc == k:
+                emitted = props + [am[k]]
+                pending = [props[k - 1], am[k]]
+                # draft consumed through d_{k-1} at base+k-1: no rewind
+                dpos = dpos_after
+            else:
+                emitted = props[:nacc] + [am[nacc]]
+                pending = [am[nacc]]
+                # draft rewind: valid through input d_nacc at base+nacc
+                lo, hi = base + nacc + 1, dpos_after
+                if hi > lo:
+                    dmask[lo:hi] = NEG_INF
+                dpos = lo
+            vpos = base + nacc + 1              # verifier valid: <= base+nacc
+            toks.extend(emitted)
+        dt = time.perf_counter() - t0
+        toks = toks[:n]
+        self.stats = {
+            "k": k, "rounds": rounds, "proposed": proposed,
+            "accepted": accepted,
+            "acceptance": round(accepted / max(proposed, 1), 4),
+            "tokens_per_round": round(len(toks) / max(rounds, 1), 3),
+            "accept_hist": hist,
+        }
+        return toks, dt, self.stats
+
+
+# ---------------- gate + bench drivers ----------------
+
+GATE_PROMPTS = {
+    "facts": "The three laws of thermodynamics state that",
+    "prose": "Once upon a time, in a quiet village by the sea,",
+    "chat": "User: How do I reverse a list in Python?\nAssistant:",
+}
+
+
+def specgate(verifier, draft, tok, k=4, lens=(32, 256), receipt=None):
+    """[G1 frozen] WITH --spec vs WITHOUT: token-identical at each length,
+    every prompt. Any mismatch = flag does not ship."""
+    sd = SpecDecoder(verifier, draft, k=k)
+    out = {"gate": "specgate", "k": k, "lens": list(lens), "prompts": {},
+           "verdict": "PASS"}
+    for name, text in GATE_PROMPTS.items():
+        ids = tok(text, add_special_tokens=False).input_ids if tok else None
+        assert ids, "specgate needs a tokenizer"
+        res = {}
+        for n in lens:
+            plain, _ = verifier.generate(ids, n)
+            spec, _, st = sd.generate(ids, n)
+            same = plain == spec
+            first = next((i for i, (a, b) in enumerate(zip(plain, spec))
+                          if a != b), -1)
+            res[str(n)] = {"identical": same, "first_divergence": first,
+                           "acceptance": st["acceptance"]}
+            if not same:
+                out["verdict"] = "FAIL"
+            print(f"  [{name} n={n}] identical={same} "
+                  f"acc={st['acceptance']:.3f}", flush=True)
+        out["prompts"][name] = res
+    if receipt:
+        json.dump(out, open(receipt, "w"), indent=1)
+        print(f"receipt -> {receipt}")
+    return out
+
+
+def specbench(verifier, draft, tok, k=4, n=512, runs=3, receipt=None):
+    """[G2 frozen] plain-8B vs 8B+draft medians, 3 text types, same process."""
+    sd = SpecDecoder(verifier, draft, k=k)
+    out = {"bench": "specbench", "k": k, "n": n, "runs": runs, "types": {}}
+    for name, text in GATE_PROMPTS.items():
+        ids = tok(text, add_special_tokens=False).input_ids
+        plain_r, spec_r, accs = [], [], []
+        for r in range(runs):
+            t, dt = verifier.generate(ids, n)
+            plain_r.append(n / dt)
+            st_toks, sdt, st = sd.generate(ids, n)
+            spec_r.append(n / sdt)
+            accs.append(st["acceptance"])
+            print(f"  [{name} run{r}] plain {plain_r[-1]:.1f} tok/s | "
+                  f"spec {spec_r[-1]:.1f} tok/s | acc {accs[-1]:.3f} | "
+                  f"tok/round {st['tokens_per_round']}", flush=True)
+        med = lambda v: sorted(v)[len(v) // 2]
+        out["types"][name] = {
+            "plain_median_tok_s": round(med(plain_r), 2),
+            "spec_median_tok_s": round(med(spec_r), 2),
+            "speedup": round(med(spec_r) / med(plain_r), 3),
+            "acceptance_median": round(med(accs), 4),
+            "plain_runs": [round(v, 2) for v in plain_r],
+            "spec_runs": [round(v, 2) for v in spec_r],
+        }
+    out["peak_mem_gib"] = round(mx.get_peak_memory() / 2**30, 2)
+    if receipt:
+        json.dump(out, open(receipt, "w"), indent=1)
+        print(f"receipt -> {receipt}")
+    return out

mlx/fermion_mlx/trit_kernels.py

@@ -0,0 +1,877 @@
+#!/usr/bin/env python3
+"""Five-value {0, +-s_lo, +-s_hi} 3-bit-planar GEMV as mx.fast.metal_kernel.
+
+Decode: per output row, three bit planes (bp=positive, bn=negative, br=high-mag),
+LSB-first. sign = p - n, magnitude selects per-row s_lo / s_hi. The kernel keeps
+two fp32 accumulators (lo/hi) so the per-row scales multiply once at the end —
+the inner loop is pure bit-extract + FMA (the Metal twin of the NEON tbl /
+CUDA PRMT decode; MSL has no byte shuffle, ALU decode is the standard move).
+
+Layout: one simdgroup per output row, SG_PER_TG simdgroups per threadgroup.
+Lanes stride uchar4 loads across the row's plane bytes; simd_sum reduction.
+
+Template flags (baked into per-shape kernel source, cached):
+  HAS_BIAS  : add fp32 bias[row]
+  FUSE_NORM : x is pre-norm; kernel computes rmsnorm(x)*g inline (g = extra input)
+  ADD_RESID : out[row] = resid[row] + y
+  GLU       : down-proj mode; x has 2*INTER entries [gate;up], col value is
+              silu(gate[c]) * up[c]  (fuses the SwiGLU elementwise pass into GEMV)
+"""
+import mlx.core as mx
+
+_HEADER = """
+static inline float trit_silu(float v) { return v / (1.0f + metal::exp(-v)); }
+"""
+
+_CACHE = {}
+
+
+def _norm_pre(cols, eps):
+    return f"""
+    float ssq = 0.0f;
+    for (uint c = lane; c < {cols}u; c += 32u) {{ float v = x[c]; ssq = metal::fma(v, v, ssq); }}
+    ssq = metal::simd_sum(ssq);
+    float rms = metal::rsqrt(ssq / {float(cols)}f + {eps:.9g}f);
+"""
+
+
+def _gemv_source(rows, cols, rs, sg_per_tg, has_bias, fuse_norm, add_resid, glu, eps):
+    """v1: per-bit scalar decode with sparsity branches."""
+    assert rs % 4 == 0, "row_stride must be multiple of 4 for uchar4 loads"
+    tail = rs * 8 != cols
+    # x effective value macro
+    if glu:
+        xv = "trit_silu(x[c]) * x[c + %d]" % cols
+        norm_pre = ""
+    elif fuse_norm:
+        xv = "x[c] * nw[c] * rms"
+        norm_pre = _norm_pre(cols, eps)
+    else:
+        xv = "x[c]"
+        norm_pre = ""
+    guard = f"if (c >= {cols}u) break;" if tail else ""
+    return f"""
+    uint tid  = thread_position_in_threadgroup.x;
+    uint lane = tid & 31u;
+    uint sg   = tid >> 5u;
+    uint row  = threadgroup_position_in_grid.x * {sg_per_tg}u + sg;
+    if (row >= {rows}u) return;
+{norm_pre}
+    const device uchar4* p4 = (const device uchar4*)bp + row * {rs // 4}u;
+    const device uchar4* n4 = (const device uchar4*)bn + row * {rs // 4}u;
+    const device uchar4* h4 = (const device uchar4*)br + row * {rs // 4}u;
+    float accLo = 0.0f, accHi = 0.0f;
+    for (uint i = lane; i < {rs // 4}u; i += 32u) {{
+        uchar4 pb = p4[i], nb = n4[i], hb = h4[i];
+        uint cb = i * 32u;
+        for (uint k = 0u; k < 4u; ++k) {{
+            uint pw = pb[k], nw2 = nb[k], hw = hb[k];
+            if ((pw | nw2) == 0u) continue;
+            for (uint j = 0u; j < 8u; ++j) {{
+                uint c = cb + k * 8u + j;
+                {guard}
+                float s = (float)((pw >> j) & 1u) - (float)((nw2 >> j) & 1u);
+                if (s == 0.0f) continue;
+                float v = s * ({xv});
+                if ((hw >> j) & 1u) accHi += v; else accLo += v;
+            }}
+        }}
+    }}
+    accLo = metal::simd_sum(accLo);
+    accHi = metal::simd_sum(accHi);
+    if (lane == 0u) {{
+        float y = metal::fma(slo[row], accLo, shi[row] * accHi);
+        {"y += bias[row];" if has_bias else ""}
+        {"y += resid[row];" if add_resid else ""}
+        out[row] = y;
+    }}
+"""
+
+
+def _gemv_source_v2(rows, cols, rs, sg_per_tg, has_bias, fuse_norm, add_resid, glu, eps):
+    """v2: branchless decode. Planes loaded as uint32 (32 weights per load),
+    per-4-bit float4 select against float4 x loads. Requires cols % 32 == 0
+    and rs % 4 == 0 with rs*8 == cols (true for all Qwen shapes)."""
+    assert rs % 4 == 0 and rs * 8 == cols and cols % 32 == 0
+    if glu:
+        xload = f"""float4 g = xg4[w * 8u + k], u = xu4[w * 8u + k];
+            float4 xv = g / (1.0f + metal::exp(-g)) * u;"""
+        norm_pre = ""
+        xpre = f"""
+    const device float4* xg4 = (const device float4*)x;
+    const device float4* xu4 = (const device float4*)(x + {cols}u);"""
+    elif fuse_norm:
+        xload = """float4 xv = x4[w * 8u + k] * nw4[w * 8u + k] * rms;"""
+        norm_pre = _norm_pre(cols, eps)
+        xpre = """
+    const device float4* x4 = (const device float4*)x;
+    const device float4* nw4 = (const device float4*)nw;"""
+    else:
+        xload = """float4 xv = x4[w * 8u + k];"""
+        norm_pre = ""
+        xpre = """
+    const device float4* x4 = (const device float4*)x;"""
+    return f"""
+    uint tid  = thread_position_in_threadgroup.x;
+    uint lane = tid & 31u;
+    uint sg   = tid >> 5u;
+    uint row  = threadgroup_position_in_grid.x * {sg_per_tg}u + sg;
+    if (row >= {rows}u) return;
+{norm_pre}{xpre}
+    const device uint* p32 = (const device uint*)bp + row * {rs // 4}u;
+    const device uint* n32 = (const device uint*)bn + row * {rs // 4}u;
+    const device uint* h32 = (const device uint*)br + row * {rs // 4}u;
+    float4 accLo4 = 0.0f, accHi4 = 0.0f;
+    for (uint w = lane; w < {rs // 4}u; w += 32u) {{
+        uint pw = p32[w], nw2 = n32[w], hw = h32[w];
+        for (uint k = 0u; k < 8u; ++k) {{
+            {xload}
+            uint sh = k * 4u;
+            float4 s = float4(float((pw >> sh) & 1u),      float((pw >> (sh+1u)) & 1u),
+                              float((pw >> (sh+2u)) & 1u), float((pw >> (sh+3u)) & 1u))
+                     - float4(float((nw2 >> sh) & 1u),      float((nw2 >> (sh+1u)) & 1u),
+                              float((nw2 >> (sh+2u)) & 1u), float((nw2 >> (sh+3u)) & 1u));
+            float4 v = s * xv;
+            bool4 hi = bool4((hw >> sh) & 1u, (hw >> (sh+1u)) & 1u,
+                             (hw >> (sh+2u)) & 1u, (hw >> (sh+3u)) & 1u);
+            accHi4 += metal::select(float4(0.0f), v, hi);
+            accLo4 += metal::select(v, float4(0.0f), hi);
+        }}
+    }}
+    float accLo = metal::simd_sum(accLo4.x + accLo4.y + accLo4.z + accLo4.w);
+    float accHi = metal::simd_sum(accHi4.x + accHi4.y + accHi4.z + accHi4.w);
+    if (lane == 0u) {{
+        float y = metal::fma(slo[row], accLo, shi[row] * accHi);
+        {"y += bias[row];" if has_bias else ""}
+        {"y += resid[row];" if add_resid else ""}
+        out[row] = y;
+    }}
+"""
+
+
+def _s8_source(rows, cols, rs, sg_per_tg, fuse_norm, eps):
+    assert rs % 4 == 0
+    if fuse_norm:
+        xv = lambda c: f"x[{c}] * nw[{c}] * rms"
+        norm_pre = f"""
+    float ssq = 0.0f;
+    for (uint c = lane; c < {cols}u; c += 32u) {{ float v = x[c]; ssq = metal::fma(v, v, ssq); }}
+    ssq = metal::simd_sum(ssq);
+    float rms = metal::rsqrt(ssq / {float(cols)}f + {eps:.9g}f);
+"""
+    else:
+        xv = lambda c: f"x[{c}]"
+        norm_pre = ""
+    assert rs * 8 >= cols and rs >= cols, "int8 record: expect row_stride >= cols"
+    nvec = cols // 4
+    return f"""
+    uint tid  = thread_position_in_threadgroup.x;
+    uint lane = tid & 31u;
+    uint sg   = tid >> 5u;
+    uint row  = threadgroup_position_in_grid.x * {sg_per_tg}u + sg;
+    if (row >= {rows}u) return;
+{norm_pre}
+    const device char* w = (const device char*)W + (ulong)row * {rs}u;
+    float acc = 0.0f;
+    for (uint i = lane * 4u; i + 3u < {cols}u; i += 128u) {{
+        char4 wv = *(const device char4*)(w + i);
+        uint c = i;
+        acc = metal::fma((float)wv.x, {xv('c')}, acc);
+        acc = metal::fma((float)wv.y, {xv('c + 1u')}, acc);
+        acc = metal::fma((float)wv.z, {xv('c + 2u')}, acc);
+        acc = metal::fma((float)wv.w, {xv('c + 3u')}, acc);
+    }}
+    acc = metal::simd_sum(acc);
+    if (lane == 0u) out[row] = scale[row] * acc;
+""" if nvec * 4 == cols else None
+
+
+SG_PER_TG = int(__import__("os").environ.get("TRIT_METAL_SGPTG", "8"))
+
+
+import os
+KERNEL_VERSION = int(os.environ.get("TRIT_METAL_V", "1"))
+RPSG = int(os.environ.get("TRIT_METAL_RPSG", "8"))
+
+
+def _gemv_source_v3(rows, cols, rs, sg_per_tg, has_bias, fuse_norm, add_resid, glu, eps,
+                    rpsg=RPSG):
+    """v3: rpsg rows per simdgroup; x (and silu/norm work) loaded once per
+    column window and reused across rows in registers — kills the per-row
+    x-reload that bound v1/v2 at ~20 GB/s. 4-wide horizontal accumulate."""
+    assert rs % 4 == 0 and rs * 8 == cols and cols % 32 == 0 and rows % rpsg == 0
+    if glu:
+        xload = f"""float4 g = xg4[w * 8u + k], u = xu4[w * 8u + k];
+            float4 xv = g / (1.0f + metal::exp(-g)) * u;"""
+        norm_pre = ""
+        xpre = f"""
+    const device float4* xg4 = (const device float4*)x;
+    const device float4* xu4 = (const device float4*)(x + {cols}u);"""
+    elif fuse_norm:
+        xload = "float4 xv = x4[w * 8u + k] * nw4[w * 8u + k] * rms;"
+        norm_pre = _norm_pre(cols, eps)
+        xpre = """
+    const device float4* x4 = (const device float4*)x;
+    const device float4* nw4 = (const device float4*)nw;"""
+    else:
+        xload = "float4 xv = x4[w * 8u + k];"
+        norm_pre = ""
+        xpre = """
+    const device float4* x4 = (const device float4*)x;"""
+    return f"""
+    uint tid  = thread_position_in_threadgroup.x;
+    uint lane = tid & 31u;
+    uint sg   = tid >> 5u;
+    uint row0 = (threadgroup_position_in_grid.x * {sg_per_tg}u + sg) * {rpsg}u;
+    if (row0 >= {rows}u) return;
+{norm_pre}{xpre}
+    const device uint* p32 = (const device uint*)bp;
+    const device uint* n32 = (const device uint*)bn;
+    const device uint* h32 = (const device uint*)br;
+    float accLo[{rpsg}], accHi[{rpsg}];
+    for (uint r = 0u; r < {rpsg}u; ++r) {{ accLo[r] = 0.0f; accHi[r] = 0.0f; }}
+    const float4 one4 = float4(1.0f);
+    for (uint w = lane; w < {rs // 4}u; w += 32u) {{
+        uint pw[{rpsg}], nw2[{rpsg}], hw[{rpsg}];
+        for (uint r = 0u; r < {rpsg}u; ++r) {{
+            ulong off = (ulong)(row0 + r) * {rs // 4}u + w;
+            pw[r] = p32[off]; nw2[r] = n32[off]; hw[r] = h32[off];
+        }}
+        for (uint k = 0u; k < 8u; ++k) {{
+            {xload}
+            uint sh = k * 4u;
+            for (uint r = 0u; r < {rpsg}u; ++r) {{
+                float4 s = float4(float((pw[r] >> sh) & 1u),      float((pw[r] >> (sh+1u)) & 1u),
+                                  float((pw[r] >> (sh+2u)) & 1u), float((pw[r] >> (sh+3u)) & 1u))
+                         - float4(float((nw2[r] >> sh) & 1u),      float((nw2[r] >> (sh+1u)) & 1u),
+                                  float((nw2[r] >> (sh+2u)) & 1u), float((nw2[r] >> (sh+3u)) & 1u));
+                float4 v = s * xv;
+                bool4 hi = bool4((hw[r] >> sh) & 1u, (hw[r] >> (sh+1u)) & 1u,
+                                 (hw[r] >> (sh+2u)) & 1u, (hw[r] >> (sh+3u)) & 1u);
+                accHi[r] += metal::dot(metal::select(float4(0.0f), v, hi), one4);
+                accLo[r] += metal::dot(metal::select(v, float4(0.0f), hi), one4);
+            }}
+        }}
+    }}
+    for (uint r = 0u; r < {rpsg}u; ++r) {{
+        float lo = metal::simd_sum(accLo[r]);
+        float hi = metal::simd_sum(accHi[r]);
+        if (lane == 0u) {{
+            uint row = row0 + r;
+            float y = metal::fma(slo[row], lo, shi[row] * hi);
+            {"y += bias[row];" if has_bias else ""}
+            {"y += resid[row];" if add_resid else ""}
+            out[row] = y;
+        }}
+    }}
+"""
+
+
+def _gemv_source_v4(rows, cols, rs, sg_per_tg, has_bias, fuse_norm, add_resid, glu, eps,
+                    rpsg=RPSG):
+    """v4: threadgroup-memory LUT decode (Metal twin of NEON vqtbl1q).
+    Per 4-column group g, lut[g][m] = sum of xv[4g+i] over set bits of m
+    (16 subset sums). Split planes on the fly into lo/hi pos/neg nibbles
+    (a=p&~h, b=n&~h, c=p&h, d=n&h): 4 weights cost 4 LUT loads + 4 adds.
+    LUT stride 17 floats kills the 16-float bank-conflict pattern. Tiled over
+    columns when the LUT would exceed threadgroup memory (down proj)."""
+    assert rs % 4 == 0 and rs * 8 == cols and cols % 32 == 0 and rows % rpsg == 0
+    # column tiling: LUT floats = tile/4*17, xbuf floats = tile -> keep <= ~26KB
+    ntiles = 1
+    while (cols // ntiles) % 32 != 0 or (cols // ntiles) * (17 / 4 + 1) * 4 > 26624:
+        ntiles += 1
+        assert ntiles <= 16
+    tile = cols // ntiles
+    gpt = tile // 4          # groups per tile
+    w0 = tile // 32          # 32-weight words per tile (per row)
+    nthreads = sg_per_tg * 32
+    if glu:
+        xv_expr = "{ float gg = x[c]; xb[cl] = gg / (1.0f + metal::exp(-gg)) * x[c + %du]; }" % cols
+    elif fuse_norm:
+        xv_expr = "xb[cl] = x[c] * nw[c] * rms;"
+    else:
+        xv_expr = "xb[cl] = x[c];"
+    if fuse_norm:
+        norm_pre = f"""
+    threadgroup float ssq_sh[{sg_per_tg}];
+    {{
+        float ssq = 0.0f;
+        for (uint c = tid; c < {cols}u; c += {nthreads}u) {{ float v = x[c]; ssq = metal::fma(v, v, ssq); }}
+        ssq = metal::simd_sum(ssq);
+        if (lane == 0u) ssq_sh[sg] = ssq;
+        threadgroup_barrier(metal::mem_flags::mem_threadgroup);
+        float t = 0.0f;
+        for (uint i = 0u; i < {sg_per_tg}u; ++i) t += ssq_sh[i];
+        rms = metal::rsqrt(t / {float(cols)}f + {eps:.9g}f);
+    }}
+"""
+    else:
+        norm_pre = ""
+    return f"""
+    uint tid  = thread_position_in_threadgroup.x;
+    uint lane = tid & 31u;
+    uint sg   = tid >> 5u;
+    uint row0 = (threadgroup_position_in_grid.x * {sg_per_tg}u + sg) * {rpsg}u;
+    float rms = 1.0f;
+{norm_pre}
+    threadgroup float xb[{tile}];
+    threadgroup float lut[{gpt} * 17];
+    const device uint* p32 = (const device uint*)bp;
+    const device uint* n32 = (const device uint*)bn;
+    const device uint* h32 = (const device uint*)br;
+    float accLo[{rpsg}], accHi[{rpsg}];
+    for (uint r = 0u; r < {rpsg}u; ++r) {{ accLo[r] = 0.0f; accHi[r] = 0.0f; }}
+    for (uint t = 0u; t < {ntiles}u; ++t) {{
+        // stage effective x for this tile
+        threadgroup_barrier(metal::mem_flags::mem_threadgroup);
+        for (uint cl = tid; cl < {tile}u; cl += {nthreads}u) {{
+            uint c = t * {tile}u + cl;
+            {xv_expr}
+        }}
+        threadgroup_barrier(metal::mem_flags::mem_threadgroup);
+        // build 16 subset sums per 4-col group
+        for (uint e = tid; e < {gpt}u * 16u; e += {nthreads}u) {{
+            uint g = e >> 4u, m = e & 15u;
+            const threadgroup float* xg = xb + g * 4u;
+            float v = 0.0f;
+            if (m & 1u) v += xg[0];
+            if (m & 2u) v += xg[1];
+            if (m & 4u) v += xg[2];
+            if (m & 8u) v += xg[3];
+            lut[g * 17u + m] = v;
+        }}
+        threadgroup_barrier(metal::mem_flags::mem_threadgroup);
+        if (row0 < {rows}u) {{
+            for (uint wl = lane; wl < {w0}u; wl += 32u) {{
+                uint w = t * {w0}u + wl;
+                for (uint r = 0u; r < {rpsg}u; ++r) {{
+                    ulong off = (ulong)(row0 + r) * {rs // 4}u + w;
+                    uint pw = p32[off], nw2 = n32[off], hw = h32[off];
+                    uint a = pw & ~hw, b = nw2 & ~hw, cc = pw & hw, d = nw2 & hw;
+                    uint gbase = wl * 8u;
+                    float lo = 0.0f, hi = 0.0f;
+                    for (uint k = 0u; k < 8u; ++k) {{
+                        const threadgroup float* lg = lut + (gbase + k) * 17u;
+                        uint sh = k * 4u;
+                        lo += lg[(a >> sh) & 15u] - lg[(b >> sh) & 15u];
+                        hi += lg[(cc >> sh) & 15u] - lg[(d >> sh) & 15u];
+                    }}
+                    accLo[r] += lo; accHi[r] += hi;
+                }}
+            }}
+        }}
+    }}
+    if (row0 >= {rows}u) return;
+    for (uint r = 0u; r < {rpsg}u; ++r) {{
+        float lo = metal::simd_sum(accLo[r]);
+        float hi = metal::simd_sum(accHi[r]);
+        if (lane == 0u) {{
+            uint row = row0 + r;
+            float y = metal::fma(slo[row], lo, shi[row] * hi);
+            {"y += bias[row];" if has_bias else ""}
+            {"y += resid[row];" if add_resid else ""}
+            out[row] = y;
+        }}
+    }}
+"""
+
+
+import os as _os
+_TILE_MAX = int(_os.environ.get("TRIT_METAL_TILE", "448"))
+
+
+def _v5_tile(cols):
+    """largest tile <= TILE_MAX with tile % 32 == 0 and cols % tile == 0."""
+    for t in range(_TILE_MAX, 31, -32):
+        if cols % t == 0 and t % 32 == 0:
+            return t
+    raise ValueError(cols)
+
+
+def _gemv_source_v5(rows, cols, rs, sg_per_tg, has_bias, fuse_norm, add_resid, glu, eps,
+                    rpsg=8):
+    """v5 = v4 LUT decode with the two occupancy/bandwidth fixes:
+    (1) planes pre-interleaved on load: uint32 words stored [row_block, word,
+        row_in_block] so a lane's 8-row load is 32 contiguous bytes (streams
+        at DRAM bandwidth; the v3/v4 scattered pattern ran at 59% of it);
+    (2) small LUT tiles (<= ~7.6KB threadgroup memory) so several threadgroups
+        fit per GPU core (v4's 19-26KB allowed only one, exposing latency).
+    Requires planes packed with pack_planes_v5. rpsg fixed at 8 by layout."""
+    assert rs % 4 == 0 and rs * 8 == cols and cols % 32 == 0 and rows % 8 == 0
+    tile = _v5_tile(cols)
+    ntiles = cols // tile
+    gpt = tile // 4
+    w0 = tile // 32
+    W = rs // 4
+    nthreads = sg_per_tg * 32
+    if glu:
+        stage = f"""
+        for (uint cl = tid; cl < {tile}u; cl += {nthreads}u) {{
+            uint c = t * {tile}u + cl;
+            float gg = x[c];
+            xb[cl] = gg / (1.0f + metal::exp(-gg)) * x[c + {cols}u];
+        }}
+        threadgroup_barrier(metal::mem_flags::mem_threadgroup);"""
+        xval = "xb[gl * 4u + i]"
+        xb_decl = f"threadgroup float xb[{tile}];"
+    elif fuse_norm:
+        stage = ""
+        xval = "x[t * %du + gl * 4u + i] * nw[t * %du + gl * 4u + i] * rms" % (tile, tile)
+        xb_decl = ""
+    else:
+        stage = ""
+        xval = "x[t * %du + gl * 4u + i]" % tile
+        xb_decl = ""
+    if fuse_norm:
+        norm_pre = f"""
+    threadgroup float ssq_sh[{sg_per_tg}];
+    {{
+        float ssq = 0.0f;
+        for (uint c = tid; c < {cols}u; c += {nthreads}u) {{ float v = x[c]; ssq = metal::fma(v, v, ssq); }}
+        ssq = metal::simd_sum(ssq);
+        if (lane == 0u) ssq_sh[sg] = ssq;
+        threadgroup_barrier(metal::mem_flags::mem_threadgroup);
+        float tt = 0.0f;
+        for (uint i = 0u; i < {sg_per_tg}u; ++i) tt += ssq_sh[i];
+        rms = metal::rsqrt(tt / {float(cols)}f + {eps:.9g}f);
+    }}
+"""
+    else:
+        norm_pre = ""
+    return f"""
+    uint tid  = thread_position_in_threadgroup.x;
+    uint lane = tid & 31u;
+    uint sg   = tid >> 5u;
+    uint blk  = threadgroup_position_in_grid.x * {sg_per_tg}u + sg;   // 8-row block
+    uint row0 = blk * 8u;
+    float rms = 1.0f;
+{norm_pre}
+    {xb_decl}
+    threadgroup float lut[{gpt} * 17];
+    const device uint* p32 = (const device uint*)bp;
+    const device uint* n32 = (const device uint*)bn;
+    const device uint* h32 = (const device uint*)br;
+    float accLo[8], accHi[8];
+    for (uint r = 0u; r < 8u; ++r) {{ accLo[r] = 0.0f; accHi[r] = 0.0f; }}
+    for (uint t = 0u; t < {ntiles}u; ++t) {{
+        threadgroup_barrier(metal::mem_flags::mem_threadgroup);
+{stage}
+        for (uint e = tid; e < {gpt}u * 16u; e += {nthreads}u) {{
+            uint gl = e >> 4u, m = e & 15u;
+            float v = 0.0f;
+            for (uint i = 0u; i < 4u; ++i)
+                if ((m >> i) & 1u) v += {xval};
+            lut[gl * 17u + m] = v;
+        }}
+        threadgroup_barrier(metal::mem_flags::mem_threadgroup);
+        if (row0 < {rows}u) {{
+            for (uint wl = lane; wl < {w0}u; wl += 32u) {{
+                uint w = t * {w0}u + wl;
+                ulong base = ((ulong)blk * {W}u + w) * 8u;   // 8 rows contiguous
+                uint gbase = wl * 8u;
+                for (uint r = 0u; r < 8u; ++r) {{
+                    uint pw = p32[base + r], nw2 = n32[base + r], hw = h32[base + r];
+                    uint a = pw & ~hw, b = nw2 & ~hw, cc = pw & hw, d = nw2 & hw;
+                    float lo = 0.0f, hi = 0.0f;
+                    for (uint k = 0u; k < 8u; ++k) {{
+                        const threadgroup float* lg = lut + (gbase + k) * 17u;
+                        uint sh = k * 4u;
+                        lo += lg[(a >> sh) & 15u] - lg[(b >> sh) & 15u];
+                        hi += lg[(cc >> sh) & 15u] - lg[(d >> sh) & 15u];
+                    }}
+                    accLo[r] += lo; accHi[r] += hi;
+                }}
+            }}
+        }}
+    }}
+    if (row0 >= {rows}u) return;
+    for (uint r = 0u; r < 8u; ++r) {{
+        float lo = metal::simd_sum(accLo[r]);
+        float hi = metal::simd_sum(accHi[r]);
+        if (lane == 0u) {{
+            uint row = row0 + r;
+            float y = metal::fma(slo[row], lo, shi[row] * hi);
+            {"y += bias[row];" if has_bias else ""}
+            {"y += resid[row];" if add_resid else ""}
+            out[row] = y;
+        }}
+    }}
+"""
+
+
+def _gemv_source_v6(rows, cols, rs, sg_per_tg, has_bias, fuse_norm, add_resid, glu, eps):
+    """v6: interleaved 8-row plane layout (pack_planes_v5) + mask-convert-fma
+    decode. For bit j of word a: (float)(a & (1<<j)) == 2^j when set, so
+    multiplying by x pre-scaled with 2^-j turns decode into AND + convert +
+    FMA (no shifts) — 4 masks (lo/hi x pos/neg) ~3.5 instr/weight, exact in
+    fp32 (power-of-two scales). x reused across the 8 rows in registers."""
+    assert rs % 4 == 0 and rs * 8 == cols and cols % 32 == 0 and rows % 8 == 0
+    W = rs // 4
+    if glu:
+        xload = f"""float4 g = xg4[w * 8u + k], u = xu4[w * 8u + k];
+            float4 xv = g / (1.0f + metal::exp(-g)) * u;"""
+        norm_pre = ""
+        xpre = f"""
+    const device float4* xg4 = (const device float4*)x;
+    const device float4* xu4 = (const device float4*)(x + {cols}u);"""
+    elif fuse_norm:
+        xload = "float4 xv = x4[w * 8u + k] * nw4[w * 8u + k] * rms;"
+        norm_pre = _norm_pre(cols, eps)
+        xpre = """
+    const device float4* x4 = (const device float4*)x;
+    const device float4* nw4 = (const device float4*)nw;"""
+    else:
+        xload = "float4 xv = x4[w * 8u + k];"
+        norm_pre = ""
+        xpre = """
+    const device float4* x4 = (const device float4*)x;"""
+    # unrolled k-body with literal masks / prescales
+    kbody = []
+    for k in range(8):
+        m = [1 << (4 * k + i) for i in range(4)]
+        ps = ", ".join("%.9ef" % (2.0 ** -(4 * k + i)) for i in range(4))
+        kbody.append(f"""        {{
+            uint k = {k}u; {xload}
+            float4 xs = xv * float4({ps});
+            const uint4 m4 = uint4({m[0]}u, {m[1]}u, {m[2]}u, {m[3]}u);
+            for (uint r = 0u; r < 8u; ++r) {{
+                uint pw = pl[r], nw2 = nl[r], hw = hl[r];
+                uint a = pw & ~hw, b = nw2 & ~hw, cc = pw & hw, d = nw2 & hw;
+                accLo[r] += metal::dot(float4(uint4(a) & m4) - float4(uint4(b) & m4), xs);
+                accHi[r] += metal::dot(float4(uint4(cc) & m4) - float4(uint4(d) & m4), xs);
+            }}
+        }}""")
+    kbody = "\n".join(kbody)
+    return f"""
+    uint tid  = thread_position_in_threadgroup.x;
+    uint lane = tid & 31u;
+    uint sg   = tid >> 5u;
+    uint blk  = threadgroup_position_in_grid.x * {sg_per_tg}u + sg;
+    uint row0 = blk * 8u;
+    if (row0 >= {rows}u) return;
+{norm_pre}{xpre}
+    const device uint* p32 = (const device uint*)bp;
+    const device uint* n32 = (const device uint*)bn;
+    const device uint* h32 = (const device uint*)br;
+    float accLo[8], accHi[8];
+    for (uint r = 0u; r < 8u; ++r) {{ accLo[r] = 0.0f; accHi[r] = 0.0f; }}
+    for (uint w = lane; w < {W}u; w += 32u) {{
+        ulong base = ((ulong)blk * {W}u + w) * 8u;
+        uint pl[8], nl[8], hl[8];
+        for (uint r = 0u; r < 8u; ++r) {{ pl[r] = p32[base+r]; nl[r] = n32[base+r]; hl[r] = h32[base+r]; }}
+{kbody}
+    }}
+    for (uint r = 0u; r < 8u; ++r) {{
+        float lo = metal::simd_sum(accLo[r]);
+        float hi = metal::simd_sum(accHi[r]);
+        if (lane == 0u) {{
+            uint row = row0 + r;
+            float y = metal::fma(slo[row], lo, shi[row] * hi);
+            {"y += bias[row];" if has_bias else ""}
+            {"y += resid[row];" if add_resid else ""}
+            out[row] = y;
+        }}
+    }}
+"""
+
+
+def _gemv_source_v7(rows, cols, rs, sg_per_tg, has_bias, fuse_norm, add_resid, glu, eps):
+    """v7: v5 interleaved layout + LUT decode with full lane utilization.
+    Lane = (row r = lane&7, word-slot = lane>>3): each lane accumulates ONE
+    row over words wslot, wslot+4, ... — all 32 lanes busy for any w0 >= 4.
+    Row sums gathered with two simd_shuffle_down folds. LUT tile 448 cols
+    (7.6KB threadgroup mem) so multiple threadgroups stay resident per core."""
+    assert rs % 4 == 0 and rs * 8 == cols and cols % 32 == 0 and rows % 8 == 0
+    tile = _v5_tile(cols)
+    ntiles = cols // tile
+    gpt = tile // 4
+    w0 = tile // 32
+    W = rs // 4
+    nthreads = sg_per_tg * 32
+    if glu:
+        stage = f"""
+        for (uint cl = tid; cl < {tile}u; cl += {nthreads}u) {{
+            uint c = t * {tile}u + cl;
+            float gg = x[c];
+            xb[cl] = gg / (1.0f + metal::exp(-gg)) * x[c + {cols}u];
+        }}
+        threadgroup_barrier(metal::mem_flags::mem_threadgroup);"""
+        xval = "xb[gl * 4u + i]"
+        xb_decl = f"threadgroup float xb[{tile}];"
+    elif fuse_norm:
+        stage = ""
+        xval = "x[t * %du + gl * 4u + i] * nw[t * %du + gl * 4u + i] * rms" % (tile, tile)
+        xb_decl = ""
+    else:
+        stage = ""
+        xval = "x[t * %du + gl * 4u + i]" % tile
+        xb_decl = ""
+    if fuse_norm:
+        norm_pre = f"""
+    threadgroup float ssq_sh[{sg_per_tg}];
+    {{
+        float ssq = 0.0f;
+        for (uint c = tid; c < {cols}u; c += {nthreads}u) {{ float v = x[c]; ssq = metal::fma(v, v, ssq); }}
+        ssq = metal::simd_sum(ssq);
+        if (lane == 0u) ssq_sh[sg] = ssq;
+        threadgroup_barrier(metal::mem_flags::mem_threadgroup);
+        float tt = 0.0f;
+        for (uint i = 0u; i < {sg_per_tg}u; ++i) tt += ssq_sh[i];
+        rms = metal::rsqrt(tt / {float(cols)}f + {eps:.9g}f);
+    }}
+"""
+    else:
+        norm_pre = ""
+    return f"""
+    uint tid  = thread_position_in_threadgroup.x;
+    uint lane = tid & 31u;
+    uint sg   = tid >> 5u;
+    uint blk  = threadgroup_position_in_grid.x * {sg_per_tg}u + sg;
+    uint row0 = blk * 8u;
+    uint r    = lane & 7u;
+    uint wsl  = lane >> 3u;
+    float rms = 1.0f;
+{norm_pre}
+    {xb_decl}
+    threadgroup float lut[{gpt} * 17];
+    const device uint* p32 = (const device uint*)bp;
+    const device uint* n32 = (const device uint*)bn;
+    const device uint* h32 = (const device uint*)br;
+    float accLo = 0.0f, accHi = 0.0f;
+    for (uint t = 0u; t < {ntiles}u; ++t) {{
+        threadgroup_barrier(metal::mem_flags::mem_threadgroup);
+{stage}
+        for (uint e = tid; e < {gpt}u * 16u; e += {nthreads}u) {{
+            uint gl = e >> 4u, m = e & 15u;
+            float v = 0.0f;
+            for (uint i = 0u; i < 4u; ++i)
+                if ((m >> i) & 1u) v += {xval};
+            lut[gl * 17u + m] = v;
+        }}
+        threadgroup_barrier(metal::mem_flags::mem_threadgroup);
+        if (row0 < {rows}u) {{
+            for (uint wl = wsl; wl < {w0}u; wl += 4u) {{
+                ulong base = ((ulong)blk * {W}u + t * {w0}u + wl) * 8u + r;
+                uint pw = p32[base], nw2 = n32[base], hw = h32[base];
+                uint a = pw & ~hw, b = nw2 & ~hw, cc = pw & hw, d = nw2 & hw;
+                uint gbase = wl * 8u;
+                for (uint k = 0u; k < 8u; ++k) {{
+                    const threadgroup float* lg = lut + (gbase + k) * 17u;
+                    uint sh = k * 4u;
+                    accLo += lg[(a >> sh) & 15u] - lg[(b >> sh) & 15u];
+                    accHi += lg[(cc >> sh) & 15u] - lg[(d >> sh) & 15u];
+                }}
+            }}
+        }}
+    }}
+    if (row0 >= {rows}u) return;
+    accLo += metal::simd_shuffle_down(accLo, 16u);
+    accLo += metal::simd_shuffle_down(accLo, 8u);
+    accHi += metal::simd_shuffle_down(accHi, 16u);
+    accHi += metal::simd_shuffle_down(accHi, 8u);
+    if (lane < 8u) {{
+        uint row = row0 + lane;
+        float y = metal::fma(slo[row], accLo, shi[row] * accHi);
+        {"y += bias[row];" if has_bias else ""}
+        {"y += resid[row];" if add_resid else ""}
+        out[row] = y;
+    }}
+"""
+
+
+def prep_planes(planes, cols=None):
+    """Trim row padding (row_stride*8 > cols in real exports; pad bits are
+    zero) so rs*8 == cols, then apply the layout transform required by the
+    active kernel version. planes = (bp, bn, br) mx.uint8 [rows, rs]."""
+    if cols is not None and cols % 8 == 0 and planes[0].shape[1] > cols // 8:
+        planes = tuple(mx.contiguous(p[:, :cols // 8]) for p in planes)
+    if KERNEL_VERSION >= 5:  # v5/v6 interleaved layout
+        return tuple(pack_planes_v5(p) for p in planes)
+    return planes
+
+
+def pack_planes_v5(plane_mx):
+    """[rows, rs] uint8 -> v5 interleaved layout (same byte count):
+    uint32 words reordered to [row_block(8), word, row_in_block]."""
+    rows, rs = plane_mx.shape
+    assert rows % 8 == 0 and rs % 4 == 0
+    w = plane_mx.view(mx.uint32).reshape(rows // 8, 8, rs // 4)
+    return mx.contiguous(w.transpose(0, 2, 1)).view(mx.uint8).reshape(rows, rs)
+
+
+def _rows_per_sg(rows, cols, rs, version, glu):
+    if version == 3 and rs % 4 == 0 and rs * 8 == cols and cols % 32 == 0 and rows % RPSG == 0:
+        return RPSG
+    return 1
+
+
+def get_trit_gemv(rows, cols, rs, has_bias=False, fuse_norm=False, add_resid=False,
+                  glu=False, eps=1e-6, version=None):
+    version = KERNEL_VERSION if version is None else version
+    if version >= 2 and not (rs % 4 == 0 and rs * 8 == cols and cols % 32 == 0):
+        version = 1  # v2+ layout preconditions not met, fall back
+    if version >= 3 and rows % (8 if version >= 5 else RPSG) != 0:
+        version = 2
+    key = ("trit", rows, cols, rs, has_bias, fuse_norm, add_resid, glu, round(eps, 12), version)
+    if key in _CACHE:
+        return _CACHE[key]
+    inputs = ["bp", "bn", "br", "slo", "shi", "x"]
+    if has_bias:
+        inputs.append("bias")
+    if fuse_norm and not glu:
+        inputs.append("nw")
+    if add_resid:
+        inputs.append("resid")
+    gen = {1: _gemv_source, 2: _gemv_source_v2, 3: _gemv_source_v3,
+           4: _gemv_source_v4, 5: _gemv_source_v5, 6: _gemv_source_v6, 7: _gemv_source_v7}[version]
+    src = gen(rows, cols, rs, SG_PER_TG, has_bias, fuse_norm, add_resid, glu, eps)
+    name = "tritgemv%d_r%d_c%d_b%d_n%d_a%d_g%d" % (version, rows, cols, has_bias, fuse_norm,
+                                                   add_resid, glu)
+    k = mx.fast.metal_kernel(name=name, input_names=inputs, output_names=["out"],
+                             source=src, header=_HEADER)
+    _CACHE[key] = (k, inputs, version)
+    return _CACHE[key]
+
+
+def _s8_source_v2(rows, cols, rs, sg_per_tg, fuse_norm, eps, rpsg=RPSG):
+    """v2 int8 GEMV: rpsg rows per simdgroup, float4 x reuse across rows."""
+    assert rs % 4 == 0 and cols % 4 == 0 and rows % rpsg == 0
+    if fuse_norm:
+        xload = "float4 xv = x4[i] * nw4[i] * rms;"
+        norm_pre = _norm_pre(cols, eps)
+        xpre = """
+    const device float4* x4 = (const device float4*)x;
+    const device float4* nw4 = (const device float4*)nw;"""
+    else:
+        xload = "float4 xv = x4[i];"
+        norm_pre = ""
+        xpre = """
+    const device float4* x4 = (const device float4*)x;"""
+    return f"""
+    uint tid  = thread_position_in_threadgroup.x;
+    uint lane = tid & 31u;
+    uint sg   = tid >> 5u;
+    uint row0 = (threadgroup_position_in_grid.x * {sg_per_tg}u + sg) * {rpsg}u;
+    if (row0 >= {rows}u) return;
+{norm_pre}{xpre}
+    float acc[{rpsg}];
+    for (uint r = 0u; r < {rpsg}u; ++r) acc[r] = 0.0f;
+    const float4 one4 = float4(1.0f);
+    for (uint i = lane; i < {cols // 4}u; i += 32u) {{
+        {xload}
+        for (uint r = 0u; r < {rpsg}u; ++r) {{
+            char4 wv = *(const device char4*)((const device char*)W
+                        + (ulong)(row0 + r) * {rs}u + i * 4u);
+            acc[r] += metal::dot(float4(wv.x, wv.y, wv.z, wv.w) * xv, one4);
+        }}
+    }}
+    for (uint r = 0u; r < {rpsg}u; ++r) {{
+        float a = metal::simd_sum(acc[r]);
+        if (lane == 0u) out[row0 + r] = scale[row0 + r] * a;
+    }}
+"""
+
+
+def get_s8_gemv(rows, cols, rs, fuse_norm=False, eps=1e-6, version=None):
+    version = KERNEL_VERSION if version is None else version
+    v = 2 if (version >= 2 and rs % 4 == 0 and cols % 4 == 0 and rows % RPSG == 0) else 1
+    key = ("s8", rows, cols, rs, fuse_norm, round(eps, 12), v)
+    if key in _CACHE:
+        return _CACHE[key]
+    inputs = ["W", "scale", "x"]
+    if fuse_norm:
+        inputs.append("nw")
+    src = (_s8_source_v2 if v == 2 else _s8_source)(rows, cols, rs, SG_PER_TG, fuse_norm, eps)
+    assert src is not None, "cols must be multiple of 4"
+    name = "s8gemv%d_r%d_c%d_n%d" % (v, rows, cols, fuse_norm)
+    k = mx.fast.metal_kernel(name=name, input_names=inputs, output_names=["out"],
+                             source=src, header=_HEADER)
+    _CACHE[key] = (k, inputs, v)
+    return _CACHE[key]
+
+
+def _grid_for(rows, rpsg=1):
+    nsg = (rows + rpsg - 1) // rpsg               # one simdgroup per rpsg rows
+    ntg = (nsg + SG_PER_TG - 1) // SG_PER_TG
+    return (ntg * SG_PER_TG * 32, 1, 1), (SG_PER_TG * 32, 1, 1)
+
+
+def trit_gemv(planes, slo, shi, x, bias=None, norm_w=None, resid=None, glu=False,
+              out_rows=None, eps=1e-6, stream=None):
+    """planes = (bp, bn, br) mx.uint8 [rows, rs]. x fp32. Returns fp32 [out_rows]."""
+    bp, bn, br = planes
+    rows, rs = bp.shape
+    out_rows = out_rows if out_rows is not None else rows
+    cols = x.shape[0] if not glu else x.shape[0] // 2
+    k, names, version = get_trit_gemv(rows, cols, rs, bias is not None, norm_w is not None,
+                                      resid is not None, glu, eps)
+    vals = {"bp": bp, "bn": bn, "br": br, "slo": slo, "shi": shi, "x": x,
+            "bias": bias, "nw": norm_w, "resid": resid}
+    grid, tg = _grid_for(out_rows, 8 if version >= 5 else (RPSG if version >= 3 else 1))
+    return k(inputs=[vals[n] for n in names], grid=grid, threadgroup=tg,
+             output_shapes=[(out_rows,)], output_dtypes=[mx.float32], stream=stream)[0]
+
+
+def s8_gemv(W, scale, x, norm_w=None, eps=1e-6, stream=None):
+    rows, rs = W.shape
+    cols = x.shape[0]
+    k, names, v = get_s8_gemv(rows, cols, rs, norm_w is not None, eps)
+    vals = {"W": W, "scale": scale, "x": x, "nw": norm_w}
+    grid, tg = _grid_for(rows, RPSG if v == 2 else 1)
+    return k(inputs=[vals[n] for n in names], grid=grid, threadgroup=tg,
+             output_shapes=[(rows,)], output_dtypes=[mx.float32], stream=stream)[0]
+
+
+# ---------------- fused rope + KV cache append ----------------
+
+def get_rope_append(n_heads, n_kv, hd, maxseq):
+    """One dispatch: rope q (n_heads*hd) and k (n_kv*hd) from the fused qkv
+    vector, write roped k and raw v in-place into the preallocated caches at
+    position pos (device scalar), output roped q. NeoX rotate-half, full hd.
+    kc/vc passed as inputs and written in place (stream-serial ordering with
+    the consumer sdpa; correctness enforced by the e2e gate)."""
+    key = ("rope_append", n_heads, n_kv, hd, maxseq)
+    if key in _CACHE:
+        return _CACHE[key]
+    qd, kd = n_heads * hd, n_kv * hd
+    h2 = hd // 2
+    src = f"""
+    uint i = thread_position_in_grid.x;              // one thread per q/k element
+    uint pos = (uint)posbuf[0];
+    device float* kc_w = (device float*)kc;
+    device float* vc_w = (device float*)vc;
+    if (i == 0u) {{ ((device float*)mask)[pos] = 0.0f; }}
+    if (i < {qd}u + {kd}u) {{
+        uint hidx = i / {hd}u, d = i % {hd}u;
+        float c = ct[pos * {h2}u + (d % {h2}u)];
+        float sn = st[pos * {h2}u + (d % {h2}u)];
+        float v = qkv[i];
+        float vrot = (d < {h2}u) ? -qkv[hidx * {hd}u + d + {h2}u]
+                                 :  qkv[hidx * {hd}u + d - {h2}u];
+        float r = metal::fma(v, c, vrot * sn);
+        if (i < {qd}u) {{
+            qout[i] = r;
+        }} else {{
+            uint kh = (i - {qd}u) / {hd}u;
+            kc_w[(ulong)(kh * {maxseq}u + pos) * {hd}u + d] = r;
+        }}
+    }} else if (i < {qd}u + 2u * {kd}u) {{
+        uint j = i - {qd}u - {kd}u;
+        uint vh = j / {hd}u, d = j % {hd}u;
+        vc_w[(ulong)(vh * {maxseq}u + pos) * {hd}u + d] = qkv[{qd}u + {kd}u + j];
+    }}
+"""
+    k = mx.fast.metal_kernel(name="rope_append_%d_%d_%d" % (n_heads, n_kv, hd),
+                             input_names=["qkv", "kc", "vc", "ct", "st", "posbuf", "mask"],
+                             output_names=["qout"], source=src)
+    _CACHE[key] = k
+    return k
+
+
+def rope_append(qkv, kc, vc, ct, st, posbuf, mask, n_heads, n_kv, hd, maxseq, stream=None):
+    k = get_rope_append(n_heads, n_kv, hd, maxseq)
+    n = (n_heads + 2 * n_kv) * hd
+    nthr = ((n + 255) // 256) * 256
+    return k(inputs=[qkv, kc, vc, ct, st, posbuf, mask], grid=(nthr, 1, 1),
+             threadgroup=(256, 1, 1),
+             output_shapes=[(n_heads * hd,)], output_dtypes=[mx.float32], stream=stream)[0]

mlx/receipts/bench_8b_wbase_m5_16gb_memcapped.json

@@ -0,0 +1,39 @@
+{
+ "mode": "bench",
+ "model": "artifacts/wbase_v4.bin",
+ "prompt_ids": [
+  785,
+  1376,
+  4522,
+  4815,
+  71617,
+  658,
+  29728,
+  14155,
+  374
+ ],
+ "gen_tokens": 128,
+ "runs": [
+  {
+   "run": 0,
+   "tokens": 128,
+   "seconds": 5.003734500001883,
+   "tok_s": 25.580893630537716
+  },
+  {
+   "run": 1,
+   "tokens": 128,
+   "seconds": 5.117534165998222,
+   "tok_s": 25.012046006542374
+  },
+  {
+   "run": 2,
+   "tokens": 128,
+   "seconds": 5.271790290993522,
+   "tok_s": 24.280176739708118
+  }
+ ],
+ "median_tok_s": 25.012046006542374,
+ "peak_mem_gib": 3.671223647892475,
+ "utc": "2026-07-25T09:38:39Z"
+}

mlx/receipts/pathgate_8b_cons3b25.json

@@ -0,0 +1,75 @@
+{
+ "n": 32,
+ "identical": true,
+ "first_divergence": null,
+ "fused": [
+  429,
+  807,
+  646,
+  4009,
+  264,
+  729,
+  448,
+  264,
+  2613,
+  1372,
+  315,
+  5029,
+  11,
+  892,
+  3643,
+  1105,
+  11050,
+  369,
+  3654,
+  9079,
+  13,
+  4354,
+  11,
+  279,
+  3491,
+  374,
+  429,
+  279,
+  1372,
+  315,
+  5029,
+  374
+ ],
+ "mxops": [
+  429,
+  807,
+  646,
+  4009,
+  264,
+  729,
+  448,
+  264,
+  2613,
+  1372,
+  315,
+  5029,
+  11,
+  892,
+  3643,
+  1105,
+  11050,
+  369,
+  3654,
+  9079,
+  13,
+  4354,
+  11,
+  279,
+  3491,
+  374,
+  429,
+  279,
+  1372,
+  315,
+  5029,
+  374
+ ],
+ "mode": "pathgate",
+ "model": "<staging>/Neutrino-8B/neutrino-8b_v4.bin"
+}

mlx/receipts/pathgate_8b_d25.json

@@ -0,0 +1,75 @@
+{
+ "n": 32,
+ "identical": true,
+ "first_divergence": null,
+ "fused": [
+  429,
+  807,
+  646,
+  387,
+  1483,
+  311,
+  4009,
+  279,
+  5480,
+  22711,
+  315,
+  264,
+  33365,
+  13,
+  576,
+  5480,
+  22711,
+  525,
+  279,
+  5128,
+  429,
+  8651,
+  2155,
+  6846,
+  304,
+  279,
+  1946,
+  3550,
+  13,
+  758,
+  264,
+  71617
+ ],
+ "mxops": [
+  429,
+  807,
+  646,
+  387,
+  1483,
+  311,
+  4009,
+  279,
+  5480,
+  22711,
+  315,
+  264,
+  33365,
+  13,
+  576,
+  5480,
+  22711,
+  525,
+  279,
+  5128,
+  429,
+  8651,
+  2155,
+  6846,
+  304,
+  279,
+  1946,
+  3550,
+  13,
+  758,
+  264,
+  71617
+ ],
+ "mode": "pathgate",
+ "model": "/tmp/neutrino-8b_v4_d25.bin"
+}

mlx/receipts/pathgate_8b_product.json

@@ -0,0 +1,75 @@
+{
+ "n": 32,
+ "identical": true,
+ "first_divergence": null,
+ "fused": [
+  429,
+  807,
+  525,
+  264,
+  943,
+  315,
+  29728,
+  3922,
+  429,
+  5711,
+  2326,
+  2155,
+  5302,
+  369,
+  1817,
+  48284,
+  13,
+  1096,
+  374,
+  2155,
+  504,
+  8606,
+  7868,
+  29728,
+  14155,
+  11,
+  892,
+  1172,
+  990,
+  1378,
+  5302,
+  320
+ ],
+ "mxops": [
+  429,
+  807,
+  525,
+  264,
+  943,
+  315,
+  29728,
+  3922,
+  429,
+  5711,
+  2326,
+  2155,
+  5302,
+  369,
+  1817,
+  48284,
+  13,
+  1096,
+  374,
+  2155,
+  504,
+  8606,
+  7868,
+  29728,
+  14155,
+  11,
+  892,
+  1172,
+  990,
+  1378,
+  5302,
+  320
+ ],
+ "mode": "pathgate",
+ "model": "/tmp/neutrino-8b_v4.bin"
+}

mlx/receipts/pathgate_8b_wbase.json

@@ -0,0 +1,75 @@
+{
+ "n": 32,
+ "identical": true,
+ "first_divergence": null,
+ "fused": [
+  429,
+  807,
+  646,
+  4009,
+  894,
+  729,
+  448,
+  264,
+  3654,
+  1372,
+  315,
+  5029,
+  11,
+  323,
+  279,
+  1372,
+  315,
+  5029,
+  374,
+  5435,
+  311,
+  279,
+  1372,
+  315,
+  7798,
+  304,
+  279,
+  3922,
+  13,
+  576,
+  1372,
+  315
+ ],
+ "mxops": [
+  429,
+  807,
+  646,
+  4009,
+  894,
+  729,
+  448,
+  264,
+  3654,
+  1372,
+  315,
+  5029,
+  11,
+  323,
+  279,
+  1372,
+  315,
+  5029,
+  374,
+  5435,
+  311,
+  279,
+  1372,
+  315,
+  7798,
+  304,
+  279,
+  3922,
+  13,
+  576,
+  1372,
+  315
+ ],
+ "mode": "pathgate",
+ "model": "artifacts/wbase_v4.bin"
+}

mlx/receipts/refgate_8b_cons3b25.json

@@ -0,0 +1,133 @@
+{
+ "ref": "/tmp/c3gate/cons3b25_ref.npz",
+ "meta": {
+  "tag": "cons3b25",
+  "donor": "Qwen/Qwen3-8B",
+  "dtype": "float32",
+  "attn": "eager",
+  "prompt": "The key idea behind ternary neural networks is",
+  "made": "2026-07-27T15:05:30Z"
+ },
+ "tf": [
+  {
+   "pos": 0,
+   "rel": 2.6224000711845977e-06,
+   "cos": 0.999999999999292,
+   "argmax_match": true
+  },
+  {
+   "pos": 1,
+   "rel": 1.9424399919302914e-06,
+   "cos": 0.9999999999994499,
+   "argmax_match": true
+  },
+  {
+   "pos": 2,
+   "rel": 1.9770419300937743e-06,
+   "cos": 0.9999999999993497,
+   "argmax_match": true
+  },
+  {
+   "pos": 3,
+   "rel": 2.279632526743816e-06,
+   "cos": 0.9999999999994535,
+   "argmax_match": true
+  },
+  {
+   "pos": 4,
+   "rel": 1.9337612922869644e-06,
+   "cos": 0.9999999999990218,
+   "argmax_match": true
+  },
+  {
+   "pos": 5,
+   "rel": 2.324533691836032e-06,
+   "cos": 0.9999999999990492,
+   "argmax_match": true
+  },
+  {
+   "pos": 6,
+   "rel": 2.616610329592598e-06,
+   "cos": 0.9999999999988447,
+   "argmax_match": true
+  },
+  {
+   "pos": 7,
+   "rel": 1.6640498515280545e-06,
+   "cos": 0.9999999999993727,
+   "argmax_match": true
+  },
+  {
+   "pos": 8,
+   "rel": 1.8894559618594419e-06,
+   "cos": 0.9999999999993779,
+   "argmax_match": true
+  }
+ ],
+ "greedy_flips": [],
+ "tie_tol": 0.04,
+ "max_flips": 8,
+ "tf_summary": {
+  "rel_max": 2.6224000711845977e-06,
+  "rel_mean": 2.1388806274506187e-06,
+  "argmax": "9/9",
+  "near_tie": 0
+ },
+ "flips": 0,
+ "worst_gap": 0.0,
+ "ok": true,
+ "mlx_greedy": [
+  429,
+  807,
+  646,
+  4009,
+  264,
+  729,
+  448,
+  264,
+  2613,
+  1372,
+  315,
+  5029,
+  11,
+  892,
+  3643,
+  1105,
+  11050,
+  369,
+  3654,
+  9079,
+  13,
+  4354,
+  11,
+  279
+ ],
+ "ref_greedy": [
+  429,
+  807,
+  646,
+  4009,
+  264,
+  729,
+  448,
+  264,
+  2613,
+  1372,
+  315,
+  5029,
+  11,
+  892,
+  3643,
+  1105,
+  11050,
+  369,
+  3654,
+  9079,
+  13,
+  4354,
+  11,
+  279
+ ],
+ "mode": "refgate",
+ "model": "neutrino-8b_v4.bin"
+}

mlx/receipts/refgate_8b_d25.json

@@ -0,0 +1,133 @@
+{
+ "ref": "/tmp/d25_ref.npz",
+ "meta": {
+  "tag": "d25",
+  "donor": "Qwen/Qwen3-8B",
+  "dtype": "float32",
+  "attn": "eager",
+  "prompt": "The key idea behind ternary neural networks is",
+  "made": "2026-07-26T09:41:51Z"
+ },
+ "tf": [
+  {
+   "pos": 0,
+   "rel": 3.7357846722178054e-06,
+   "cos": 0.9999999999992958,
+   "argmax_match": true
+  },
+  {
+   "pos": 1,
+   "rel": 1.9618753776610103e-06,
+   "cos": 0.9999999999994419,
+   "argmax_match": true
+  },
+  {
+   "pos": 2,
+   "rel": 1.8195449731555086e-06,
+   "cos": 0.999999999999342,
+   "argmax_match": true
+  },
+  {
+   "pos": 3,
+   "rel": 2.111957507414951e-06,
+   "cos": 0.999999999999451,
+   "argmax_match": true
+  },
+  {
+   "pos": 4,
+   "rel": 1.8725257620352456e-06,
+   "cos": 0.9999999999988299,
+   "argmax_match": true
+  },
+  {
+   "pos": 5,
+   "rel": 1.8537546715748062e-06,
+   "cos": 0.9999999999990721,
+   "argmax_match": true
+  },
+  {
+   "pos": 6,
+   "rel": 1.8210546698822445e-06,
+   "cos": 0.9999999999988646,
+   "argmax_match": true
+  },
+  {
+   "pos": 7,
+   "rel": 1.8684000228879002e-06,
+   "cos": 0.9999999999994065,
+   "argmax_match": true
+  },
+  {
+   "pos": 8,
+   "rel": 1.9054552787661224e-06,
+   "cos": 0.9999999999993701,
+   "argmax_match": true
+  }
+ ],
+ "greedy_flips": [],
+ "tie_tol": 0.04,
+ "max_flips": 8,
+ "tf_summary": {
+  "rel_max": 3.7357846722178054e-06,
+  "rel_mean": 2.105594770621733e-06,
+  "argmax": "9/9",
+  "near_tie": 0
+ },
+ "flips": 0,
+ "worst_gap": 0.0,
+ "ok": true,
+ "mlx_greedy": [
+  429,
+  807,
+  646,
+  387,
+  1483,
+  311,
+  4009,
+  279,
+  5480,
+  22711,
+  315,
+  264,
+  33365,
+  13,
+  576,
+  5480,
+  22711,
+  525,
+  279,
+  5128,
+  429,
+  8651,
+  2155,
+  6846
+ ],
+ "ref_greedy": [
+  429,
+  807,
+  646,
+  387,
+  1483,
+  311,
+  4009,
+  279,
+  5480,
+  22711,
+  315,
+  264,
+  33365,
+  13,
+  576,
+  5480,
+  22711,
+  525,
+  279,
+  5128,
+  429,
+  8651,
+  2155,
+  6846
+ ],
+ "mode": "refgate",
+ "model": "/tmp/neutrino-8b_v4_d25.bin"
+}

mlx/receipts/refgate_8b_product.json

@@ -0,0 +1,133 @@
+{
+ "ref": "/tmp/s50_ref.npz",
+ "meta": {
+  "tag": "s50",
+  "donor": "Qwen/Qwen3-8B",
+  "dtype": "float32",
+  "attn": "eager",
+  "prompt": "The key idea behind ternary neural networks is",
+  "made": "2026-07-26T00:09:27Z"
+ },
+ "tf": [
+  {
+   "pos": 0,
+   "rel": 2.7188532122724473e-06,
+   "cos": 0.9999999999992888,
+   "argmax_match": true
+  },
+  {
+   "pos": 1,
+   "rel": 2.1881101921352207e-06,
+   "cos": 0.9999999999994555,
+   "argmax_match": true
+  },
+  {
+   "pos": 2,
+   "rel": 2.319768487104987e-06,
+   "cos": 0.999999999999356,
+   "argmax_match": true
+  },
+  {
+   "pos": 3,
+   "rel": 1.8684499152657963e-06,
+   "cos": 0.9999999999994532,
+   "argmax_match": true
+  },
+  {
+   "pos": 4,
+   "rel": 1.8324882362981365e-06,
+   "cos": 0.9999999999979642,
+   "argmax_match": true
+  },
+  {
+   "pos": 5,
+   "rel": 2.1302047849215587e-06,
+   "cos": 0.9999999999989747,
+   "argmax_match": true
+  },
+  {
+   "pos": 6,
+   "rel": 2.7137296248146236e-06,
+   "cos": 0.9999999999988849,
+   "argmax_match": true
+  },
+  {
+   "pos": 7,
+   "rel": 1.7059300688086893e-06,
+   "cos": 0.9999999999993904,
+   "argmax_match": true
+  },
+  {
+   "pos": 8,
+   "rel": 1.9090595614651556e-06,
+   "cos": 0.9999999999993883,
+   "argmax_match": true
+  }
+ ],
+ "greedy_flips": [],
+ "tie_tol": 0.04,
+ "max_flips": 8,
+ "tf_summary": {
+  "rel_max": 2.7188532122724473e-06,
+  "rel_mean": 2.154066009231846e-06,
+  "argmax": "9/9",
+  "near_tie": 0
+ },
+ "flips": 0,
+ "worst_gap": 0.0,
+ "ok": true,
+ "mlx_greedy": [
+  429,
+  807,
+  525,
+  264,
+  943,
+  315,
+  29728,
+  3922,
+  429,
+  5711,
+  2326,
+  2155,
+  5302,
+  369,
+  1817,
+  48284,
+  13,
+  1096,
+  374,
+  2155,
+  504,
+  8606,
+  7868,
+  29728
+ ],
+ "ref_greedy": [
+  429,
+  807,
+  525,
+  264,
+  943,
+  315,
+  29728,
+  3922,
+  429,
+  5711,
+  2326,
+  2155,
+  5302,
+  369,
+  1817,
+  48284,
+  13,
+  1096,
+  374,
+  2155,
+  504,
+  8606,
+  7868,
+  29728
+ ],
+ "mode": "refgate",
+ "model": "/tmp/neutrino-8b_v4.bin"
+}

mlx/receipts/refgate_8b_wbase.json

@@ -0,0 +1,133 @@
+{
+ "ref": "artifacts/wbase_ref.npz",
+ "meta": {
+  "tag": "wbase",
+  "donor": "Qwen/Qwen3-8B",
+  "dtype": "float32",
+  "attn": "eager",
+  "prompt": "The key idea behind ternary neural networks is",
+  "made": "2026-07-25T05:16:03Z"
+ },
+ "tf": [
+  {
+   "pos": 0,
+   "rel": 2.5888214527867327e-06,
+   "cos": 0.9999999999993819,
+   "argmax_match": true
+  },
+  {
+   "pos": 1,
+   "rel": 2.474946032917843e-06,
+   "cos": 0.9999999999994814,
+   "argmax_match": true
+  },
+  {
+   "pos": 2,
+   "rel": 2.3891665631361155e-06,
+   "cos": 0.9999999999993758,
+   "argmax_match": true
+  },
+  {
+   "pos": 3,
+   "rel": 2.329101721715938e-06,
+   "cos": 0.9999999999994569,
+   "argmax_match": true
+  },
+  {
+   "pos": 4,
+   "rel": 1.6647379290477042e-06,
+   "cos": 0.9999999999984548,
+   "argmax_match": true
+  },
+  {
+   "pos": 5,
+   "rel": 2.36762622893542e-06,
+   "cos": 0.9999999999989674,
+   "argmax_match": true
+  },
+  {
+   "pos": 6,
+   "rel": 1.7604135798303548e-06,
+   "cos": 0.9999999999987743,
+   "argmax_match": true
+  },
+  {
+   "pos": 7,
+   "rel": 1.7215424255002515e-06,
+   "cos": 0.9999999999994331,
+   "argmax_match": true
+  },
+  {
+   "pos": 8,
+   "rel": 1.7872186699375681e-06,
+   "cos": 0.9999999999993865,
+   "argmax_match": true
+  }
+ ],
+ "greedy_flips": [],
+ "tie_tol": 0.04,
+ "max_flips": 8,
+ "tf_summary": {
+  "rel_max": 2.5888214527867327e-06,
+  "rel_mean": 2.120397178200881e-06,
+  "argmax": "9/9",
+  "near_tie": 0
+ },
+ "flips": 0,
+ "worst_gap": 0.0,
+ "ok": true,
+ "mlx_greedy": [
+  429,
+  807,
+  646,
+  4009,
+  894,
+  729,
+  448,
+  264,
+  3654,
+  1372,
+  315,
+  5029,
+  11,
+  323,
+  279,
+  1372,
+  315,
+  5029,
+  374,
+  5435,
+  311,
+  279,
+  1372,
+  315
+ ],
+ "ref_greedy": [
+  429,
+  807,
+  646,
+  4009,
+  894,
+  729,
+  448,
+  264,
+  3654,
+  1372,
+  315,
+  5029,
+  11,
+  323,
+  279,
+  1372,
+  315,
+  5029,
+  374,
+  5435,
+  311,
+  279,
+  1372,
+  315
+ ],
+ "mode": "refgate",
+ "model": "artifacts/wbase_v4.bin"
+}

mlx/receipts/specbench_8b_0p6b_m5.json

@@ -0,0 +1,57 @@
+{
+ "bench": "specbench",
+ "k": 4,
+ "n": 512,
+ "runs": 3,
+ "types": {
+  "facts": {
+   "plain_median_tok_s": 22.0,
+   "spec_median_tok_s": 25.71,
+   "speedup": 1.168,
+   "acceptance_median": 0.7442,
+   "plain_runs": [
+    23.52,
+    22.0,
+    21.08
+   ],
+   "spec_runs": [
+    26.3,
+    25.71,
+    23.76
+   ]
+  },
+  "prose": {
+   "plain_median_tok_s": 17.86,
+   "spec_median_tok_s": 12.15,
+   "speedup": 0.68,
+   "acceptance_median": 0.2994,
+   "plain_runs": [
+    19.12,
+    17.86,
+    17.84
+   ],
+   "spec_runs": [
+    12.48,
+    12.1,
+    12.15
+   ]
+  },
+  "chat": {
+   "plain_median_tok_s": 17.53,
+   "spec_median_tok_s": 14.68,
+   "speedup": 0.837,
+   "acceptance_median": 0.4395,
+   "plain_runs": [
+    17.72,
+    17.53,
+    17.35
+   ],
+   "spec_runs": [
+    15.01,
+    14.67,
+    14.68
+   ]
+  }
+ },
+ "peak_mem_gib": 4.3
+}

mlx/receipts/specgate_8b_0p6b.json

@@ -0,0 +1,47 @@
+{
+ "gate": "specgate",
+ "k": 4,
+ "lens": [
+  32,
+  256
+ ],
+ "prompts": {
+  "facts": {
+   "32": {
+    "identical": true,
+    "first_divergence": -1,
+    "acceptance": 0.3214
+   },
+   "256": {
+    "identical": true,
+    "first_divergence": -1,
+    "acceptance": 0.6714
+   }
+  },
+  "prose": {
+   "32": {
+    "identical": true,
+    "first_divergence": -1,
+    "acceptance": 0.4038
+   },
+   "256": {
+    "identical": true,
+    "first_divergence": -1,
+    "acceptance": 0.2896
+   }
+  },
+  "chat": {
+   "32": {
+    "identical": true,
+    "first_divergence": -1,
+    "acceptance": 0.55
+   },
+   "256": {
+    "identical": true,
+    "first_divergence": -1,
+    "acceptance": 0.4289
+   }
+  }
+ },
+ "verdict": "PASS"
+}